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US4775932A Expired / Lapsed US ⏱️ 0.0 years remaining

Computer memory system with parallel garbage collection independent from an associated user processor

Assignee: Texas Instruments Inc
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Filing: 1984-07-31
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Granted: 1988-10-04
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Expires: 2004-07-31
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Abstract

Abstract A memory system for association with a user processor for operation independently from the user processor includes a physical memory and an interface unit for enabling the associated user processor to access the physical memory. The physical memory is represented in a virtual address space which is garbage collected in parallel with the operation of the user processor. The garbage collection process includes reference count deallocation and a garbage collection algorithm for deallocating cyclic structures not deallocated by the reference count process. The reference count process includes providing for a reference count indicating the number of pointer references to a memory block in the virtual address space. When the reference count becomes zero, and no other references to a memory block exist, the block may be freed. In the garbage collection algorithm, the virtual memory space is traced in areas, called OLDSPACE, and compactly copied into a new area, called NEWSPACE. The OLDSPACE and NEWSPACE are further scavenged to insure that all referenced blocks of memory are copied, and the remaining OLDSPACE is cleaned. The garbage collection process is performed in parallel with the operation of the user processor.

Inventors

  • 👤 Donald W. Oxley
  • 👤 Timothy J. McEntee
  • 👤 Satish M. Thatte

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-24 09:47
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/0223; G06F12/023; G06F12/0253; G06F12/0261; Y; Y10; Y10S; Y10S707/00; Y10S707/99951; Y10S707/99956; Y10S707/99957

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 165 words
A memory system for use with a user processor, comprising: a physical memory; a binding register unit having a plurality of registers accessed by the user processor, said registers containing only identifiers for blocks of memory and data, wherein said binding register unit enables relative location indexing by the user processor for data manipulation; means independent from the user processor for managing the physical memory and binding register unit, wherein the memory system functions as a collection of user specified blocks accessed only through the binding register unit; computer program means for controlling the physical memory; and binding register managing means for performing garbage collection of a virtual address space representing the physical memory independently from and in parallel with the operation of the user processor, wherein all blocks which cannot be reached by following pointers directly or indirectly from any binding register are garbage, and all blocks which can be reached by following pointers directly or indirectly from any binding register are not garbage.
Claim 2
Dependent Claim 165 words
A memory system for use with a user processor, comprising: a physical memory; a binding register unit having a plurality of registers accessed by the user processor, said registers containing only identifiers for blocks of memory and data, wherein said binding register unit enables relative location indexing by the user processor for data manipulation; means independent from the user processor for managing the physical memory and binding register unit, wherein the memory system functions as a collection of user specified blocks accessed only through the binding register unit; computer program means for controlling the physical memory; and binding register managing means for performing garbage collection of a virtual address space representing the physical memory independently from and in parallel with the operation of the user processor, wherein all blocks which cannot be reached by following pointers directly or indirectly from any binding register are garbage, and all blocks which can be reached by following pointers directly or indirectly from any binding register are not garbage.
Claim 3
Dependent Claim 138 words
A memory system for use with a central processor of a computer system, comprising: a plurality of binding registers, wherein the central processor accesses memory only by reference to a binding register and an offset value; a physical memory having an address space; a memory manager having a memory processor, wherein said memory manager translates references to binding registers and offsets by the central processor into addresses in said physical memory; and a garbage collector in said memory manager and operated by the memory processor, wherein said garbage collector identifies regions of memory which are no longer accessible to the central processor and releases them for use by the memory manager, and wherein all regions accessible to the central processor consist of those regions which can be reached directly or indirectly by following pointers from any binding register
Claim 4
Dependent Claim 138 words
A memory system for use with a central processor of a computer system, comprising: a plurality of binding registers, wherein the central processor accesses memory only by reference to a binding register and an offset value; a physical memory having an address space; a memory manager having a memory processor, wherein said memory manager translates references to binding registers and offsets by the central processor into addresses in said physical memory; and a garbage collector in said memory manager and operated by the memory processor, wherein said garbage collector identifies regions of memory which are no longer accessible to the central processor and releases them for use by the memory manager, and wherein all regions accessible to the central processor consist of those regions which can be reached directly or indirectly by following pointers from any binding register

References Cited (Backward Citations)

US4123795A Cited
US3882470A Cited
US4189773A Cited
US4121286A Cited
US4446516A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1991-10-04 1992-04-04 1992-10-04 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1995-10-04 1996-04-04 1996-10-04 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1999-10-04 2000-04-04 2000-10-04 $7700.00 Window Closed / Lapsed

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