Integrated circuit having capacitive process-scatter compensation

Claim 2

An integrated circuit comprising at least one logic gate circuit having at least one node, which is to be charged and discharged under the control of a logic signal, a reference voltage-controlled switching element, a capacitance coupled to said node via said reference voltage-controlled switching element, and control means for supplying said reference voltage as a function of the manufacturing process to compensate for a manufacturing process-induced spread in charge and discharge times of said node.

Claim 3

An integrated circuit as claimed in claim 1, comprising insulated gate field-effect transistors, the capacitance comprising a depletion type field-effect transistor connected as a capacitor, and the switching element comprising an enhancement type field-effect transistor receiving the reference voltage on its gate.

Claim 4

An integrated circuit as claimed in claim 2, comprising, between a first and second supply terminal, a first and a second current branch mutually cross-coupled via a respective transistor, having a conduction channel in the respective current branch, whereby at least one current branch comprises a series arrangement of conduction channels of transistors, each interconnecting node between a pair of conduction channels in said series arrangement being connected via a switching element to an additional capacitance, each switching element receiving the same reference voltage.

Claim 5

An integrated circuit as claimed in claim 3, wherein the circuit contains a first and a second current branch, the first current branch containing a first field-effect transistor of the depletion type of which the conduction channel is connected between a first supply terminal and an inverting output, and second through eighth field-effect transistors, the gate of said first transistor being connected to said output, and in which the first current branch further contains a first internal node which is connected via the conduction channel of said second field-effect transistor of the enhancement type to the inverting output and via parallel channels of said third and a fourth field-effect transistor of the enhancement type to a second supply terminal, the gate of the third transistor receiving the clock signal and the gate of the fourth field-effect transistor being connected to a first input, the second current branch containing said fifth field-effect transistor of the depletion type which connects the first supply terminal to a non-inverting output, its gate being connected to the latter output; the second current branch further containing a second internal node, which is connected via the conduction channel of said sixth field-effect transistor of the depletion type to the non-inverting output and is connected via parallel channels of said seventh and eighth field-effect transistors of the enhancement type to the second supply terminal, the gate of the seventh field-effect transistor receiving the clock signal and the gate of the eighth transistor being connected to a second input, the gate of the second field-effect transistor further being connected to the non-inverting output and the gate of the sixth field-effect transistor being connected to the inverting output, the first and the second internal node each being connected to the second supply terminal via a series arrangement of a ninth field-effect transistor serving as the additional capacitance and a tenth field-effect transistor serving as the switching element.

Claim 6

An integrated circuit as claimed in claim 2, 3 or 4, the control means comprising a depletion type field-effect upper transistor, having a first main electrode connected to a high voltage supply terminal and having a gate electrode connected to a low voltage supply terminal, at least one diode-connected enhancement type field-effect transistor having a conduction channel inserted in a path between a second main electrode of the upper transistor and a resistive load element that is connected to the low voltage supply terminal, the reference voltage being transmitted on an output terminal between the load element and the diode-connected transistor.

Claim 7

An integrated circuit as claimed in claim 2, 3 or 4, the control means comprising a depletion type field-effect upper transistor, having a first main electrode connected to high voltage supply terminal and having a gate electrode connected to a low voltage supply terminal, at least one diode-connected enhancement type field-effect transistor having a conduction channel inserted in a path between a second main electrode of the upper transistor and a resistive load element that is connected to the low voltage supply terminal, the reference voltage being transmitted on an output terminal between the load element and the diode-connected transistor, the resistive load element comprising a further depletion type field-effect transistor connected as a current source.

Claim 8

An integrated circuit as claimed in claim 1, comprising complementary insulated gate field-effect transistors, the additional capacitance comprising a P-channel field-effect transistor having its main electrodes coupled to the higher of two circuit supply voltages, the switching element comprising a N-channel field-effect transistor receiving the reference voltage on its gate.

Claim 9

An integrated circuit as claimed in claim 7, comprising a first and a second current branch between a first and second supply terminal and mutually cross-coupled via a respective transistor having its conduction channel inserted in the respective current branch, whereby at least one current branch comprises a series arrangement of conduction channels of transistors, each interconnecting node between a pair of conduction channels in said series arrangement being connected via a relative switching element to an additional capacitance, each switching element receiving the same reference voltage.

Claim 10

An integrated circuit as claimed in claim 8, comprising complementary field-effect transistors, whereby the circuit comprises a first and a second current branch, each of which contains an input and an output node, the output node being connected to a first supply terminal via the series connected conduction channels of a respective first and a respective second PMOS transistor and the conduction channel of a respective third PMOS transistor connected in parallel to this series arrangement, the output node further being connected to the second supply terminal V SS via the parallel-connected conduction channels of a respective first and a respective second NMOS transistor and the conduction channel of a respective third NMOS transistor connected in series thereto, the gates of the second PMOS and NMOS transistors being connected to a clock input; the gates of the third PMOS and NMOS transistors are connected in the first current branch to a SET input and in the second current branch to a RESET input, each current branch further being provided with a PMOS transistor serving as a capacitance, its main electrodes being connected to the first supply voltage and its gate being connected via the conduction channel of an NMOS transistor serving as a switching element to the conduction channels of the first, second and third NMOS transistors, the input node of the first current branch being connected to the output node of the second current branch and the input node of the second current branch being connected to the output node of the first current branch, the gates of the transistor serving as switching elements being interconnected for receiving the reference voltage.

Claim 11

An integrated circuit as claimed in claim 7, 8 or 9, the control means comprising, between a high voltage supply terminal and a reference voltage output, a series arrangement of at least one diode-connected N-channel field-effect transistor, and a resistive load element, connected between said reference voltage output and a low voltage supply terminal.

Claim 12

An integrated circuit as claimed in claim 10, the control means comprising, between a high voltage supply terminal and a reference voltage output, a series arrangement of at least one diode-connected N-channel field-effect transistor and connected between said reference voltage output and a low voltage supply terminal a diode-connected P-channel field-effect transistor.

Claim 13

Control means for generating a process-dependent reference voltage, comprising a depletion type field-effect upper transistor, having a first main electrode connected to high voltage supply terminal and having a gate electrode connected to a low voltage supply terminal, at least one diode-connected enhancement type field-effect transistor having a conduction channel inserted in a path between a second main electrode of the upper transistor and a resistive load element connected to the low voltage supply terminal, the reference voltage being transmitted on an output terminal between the load element and the diode-connected transistor.

Claim 14

Control means for generating a process-dependent reference voltage, comprising a depletion type field-effect upper transistor, having a first main electrode connected to high voltage supply terminal and having a gate electrode connected to a low voltage supply terminal, at least one diode-connected enhancement type field-effect transistor having a conduction channel inserted in a path between a second main electrode of the upper transistor and a resistive load element connected to the low voltage supply terminal, the reference voltage being transmitted on an output terminal between the load element and the diode-connected transistor.

Claim 15

Control means for generating a process-dependent reference voltage as claimed in claim 12, the resistive load element comprising a further depletion type field-effect transistor connected as a current source.

Claim 16

Control means for generating a process-dependent reference voltage comprising, between a high voltage supply terminal and a reference voltage output, a series arrangement of at least one diode-connected N-channel field-effect transistor, and a resistive load element, connected between said reference voltage output and a low voltage supply terminal.

Claim 17

Control means for generating a process-dependent reference voltage comprising, between a high voltage supply terminal and a reference voltage output, a series arrangement of at least one diode-connected N-channel field-effect transistor, and a resistive load element, connected between said reference voltage output and a low voltage supply terminal.

Claim 18

Control means for generating a process-dependent reference voltage as claimed in claim 14 the resistive load element comprising a diode-connected P-channel field-effect transistor.