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US4773045A Expired / Lapsed US ⏱️ 0.0 years remaining

Semiconductor memory device with shift during write capability

Assignee: Fujitsu Ltd
•
Filing: 1985-10-16
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Granted: 1988-09-20
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Expires: 2005-10-16
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Abstract

Abstract A semiconductor memory device including a RAM portion and a shift register for enabling parallel transfer of a one word line amount of data of the RAM portion between the RAM portion and the shift register. The shift register is divided into a plurality of shift register portions with serial input data being distributed alternately between the shift register portions by the operation of a multiplexer and serial output data being obtained by picking up data alternately from the shift register portions by the operation of another multiplexer. A transfer gate portion is inserted between the RAM portion and the shift register for carrying out parallel transfer, the transfer gate portion includes a plurality of groups of transfer gates for enabling selective connections of input and output terminals of each of the stages of the shift register portions with either of the adjacent odd numbered bit line and even numbered bit line of the RAM portion. The plurality of transfer gate groups are switched in correspondence with shift clock signals.

Inventors

  • 👤 Junji Ogawa

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-04 23:46
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C7/00; G11C7/10; G11C7/1015; G11C7/1036; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4096; G11C7/1006

Claims Analysis

Total Claims: 3
Claim 1
Independent Claim 177 words
A semiconductor memory device, comprising: a random access memory portion including a plurality of first and second columns; first and second shift registers, operatively connected to said random access memory portion, for serially inputting into or outputting from said device and enabling parallel transfer, of a one word line amount of data of said random access memory portion, each shift register being devided into a plurality of shift register stages; first and second transfer gate portions, operatively connected between said random access memory portion and said shift registers, for carrying out parallel transfer therebetween, each of said first and second transfer gate portions including a plurality of groups of direct and shift transfer gates, said shift register stages of said first shift register being connected to said first columns by said direct transfer gates, respectively, and to said second columns via said shift transfer gates, respectively said shift register stages of said second shift register being connected to said second columns by said direct transfer gates, respectively, and to said first columns by said shift transfer gates.
Claim 2
Dependent Claim 177 words
A semiconductor memory device, comprising: a random access memory portion including a plurality of first and second columns; first and second shift registers, operatively connected to said random access memory portion, for serially inputting into or outputting from said device and enabling parallel transfer, of a one word line amount of data of said random access memory portion, each shift register being devided into a plurality of shift register stages; first and second transfer gate portions, operatively connected between said random access memory portion and said shift registers, for carrying out parallel transfer therebetween, each of said first and second transfer gate portions including a plurality of groups of direct and shift transfer gates, said shift register stages of said first shift register being connected to said first columns by said direct transfer gates, respectively, and to said second columns via said shift transfer gates, respectively said shift register stages of said second shift register being connected to said second columns by said direct transfer gates, respectively, and to said first columns by said shift transfer gates.
Claim 3
Dependent Claim 43 words
A memory device as recited in claim 1, wherein said direct transfer gates comprise transistors connected between stages of said shift register and said columns, and said shift transfer gates comprise transistors connected between the stages of said shift register and said columns.

References Cited (Backward Citations)

US4151609A Cited
US4281401A Cited
JPS5698785A Cited
US4321695A Cited
US4330852A Cited
US4347587A Cited
WO1982002615A1 Cited
US4616343A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1991-09-20 1992-03-21 1992-09-20 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1995-09-20 1996-03-21 1996-09-20 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1999-09-20 2000-03-21 2000-09-20 $7700.00 Window Closed / Lapsed

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