Pipelined data processing system utilizing ideal floating point execution condition detection

Claim 2

An instruction execution unit responsive to an instruction for providing a sequence of microcode control words to direct the processing of operand data associated with said instruction, said instruction execution unit comprising: (a) sequencing means, responsive to said instruction, for issuing first and second sequences of microcode control words corresponding to said instruction, said sequencing means including selector means for selecting said first or said second sequence of microcode control words for issuance by said sequencing means; and (b) determining means for determining from said operand data, concurrent with the issuance of a microcode control word by said sequencing means, whether said operand data is ideal with respect to said instruction, said determining means causing said selector means to select said second sequence of microcode control words for issuance to complete the processing of said operand data in response to said instruction when said operand data is ideal with respect to said instruction.

Claim 3

The instruction execution unit of claim 1 wherein said instruction is a floating point instruction, wherein said first sequence of microcode control words include microcode control words for detecting and controlling the occurrence of underflow and overflow conditions in the processing of non-ideal floating point instruction operand data and wherein said second sequence of microcode control words excludes microcode control words for detecting and controlling the occurrence of underflow and overflow conditions in the processing of floating point operand data associated with said instruction.

Claim 4

The unit of claim 2 wherein said sequencing means comprises: (a) a control store including storage means for storing a sequence of microcode control word; (b) a control store address register including means for receiving a selected address pointer from said selector means and for applying said address pointer to said storage means; (c) a control word latch including means for receiving a control word corresponding to said address pointer; and (d) primitive operator means, coupled to said control word latch for receiving said control word, for performing a corresponding floating point primitive point operation on said operand data, said control word identifying the one of a plurality of floating point primitive operation including non-ideal floating point primitive operations wherein the non-ideal condition of said operand data with respect to said instruction is detected, said primitive operator means performing each floating point primitive operation identified by a corresponding said control word in a respective machine cycle.

Claim 5

The unit of claim 3 wherein said selector means provides a branch address pointer to said control store address register, said selecting means, in response to the determination made by said determining means, enabling said receiving means of said control store address register to receive said branch address pointer.

Claim 6

The unit of claim 4 further comprising an ideal condition latch responsive to said determining means for storing a signal representative of the determination made by said determining means.

Claim 7

The unit of claim 5 wherein said selector means is connected to said ideal condition latch and responsive to the signal provided thereby.

Claim 8

The unit of claim 2 or 6 wherein said operand data includes two operands, each of said operands including an operand fraction having a plurality of digits and an operand exponent, said determining means comprises: (a) first means for predicting the occurrence of an underflow, recomplement or zero condition from said operand data with respect to said instruction, said first means including: (i) first logic means for detecting whether the operand fractions are added and whether the one of said operands with the larger magnitude is normalized; (ii) second logic means for detecting whether the one of said operands with the larger magnitude is normalized, whether the operand exponents are unequal, and whether the larger operand exponent has a value of at least `10` Hex; and (iii) third logic means for detecting whether the one of said operands with the larger magnitude is normalized, whether the leading digits of the operand fraction of each of said operands are unequal, and whether the larger operand exponent has a value of at least `10` Hex; and (b) second means for predicting the occurrence of an overflow condition from said operand data with respect to said instruction, said second means including: (i) fourth logic means for detecting whether the operand fractions are subtracted; and (ii) fifth logic means for detecting whether both operand exponents have a value less than `7F` Hex.

Claim 9

The unit of claim 7 wherein said determining means further comprises: (a) third means for predicting the occurrence of an underflow condition from said operand data with respect to said instruction, said third means including: (i) sixth logic means for detecting whether both of said operands are normalized and whether the sum of the operand exponents is at least `41` Hex; and (ii) seventh logic means for detecting whether the sum of the operand exponents is less than `CO` Hex.

Claim 10

The unit of claim 8 wherein said determining means determines that said operand data is ideal with respect to said instruction when said instruction is a floating point addition or subtraction instruction and if said first, second or third logic means evaluates true and said fourth or fifth logic means evaluates true.

Claim 11

The unit of claim 8 wherein said determining means determines that said operand data is ideal with respect to said instruction when said instruction is a floating point multiplication instruction and if said sixth and seventh logic means evaluate true.

Claim 12

The unit of claim 8 wherein said instruction is also ideal if said instruction is also a floating point compare instruction and if said first, second, and third logic means evaluate true.

Claim 15

An instruction execution unit responsive to an instruction for processing operand data comprising: (a) determining means for determining from said operand data whether said operand data is ideal with respect to said instruction; (b) primitive operator means for performing a plurality of floating point primitive operations on said operand data including non-ideal primitive operations wherein non-ideal conditions are detected and dealt with, said primitive operator means performing each primitive operation in a respective machine cycle; (c) sequencing means, responsive to said instruction, for controlling said primitive operator means to perform sequences, each sequence including a plurality of primitive operations in a respective plurality of said machine cycles, to execute said instruction and at least one of said sequences not including non-ideal primitive operations; and (d) selector means, connected to said sequencing means and responsive to said determining means, for selecting said one of said sequences not including non-ideal primitive operations whereby the number of machine cycles utilized in the execution of said instruction is reduced when said operand data is ideal with respect to said instruction.

Claim 16

An instruction execution unit responsive to an instruction for processing operand data comprising: (a) determining means for determining from said operand data whether said operand data is ideal with respect to said instruction; (b) primitive operator means for performing a plurality of floating point primitive operations on said operand data including non-ideal primitive operations wherein non-ideal conditions are detected and dealt with, said primitive operator means performing each primitive operation in a respective machine cycle; (c) sequencing means, responsive to said instruction, for controlling said primitive operator means to perform sequences, each sequence including a plurality of primitive operations in a respective plurality of said machine cycles, to execute said instruction and at least one of said sequences not including non-ideal primitive operations; and (d) selector means, connected to said sequencing means and responsive to said determining means, for selecting said one of said sequences not including non-ideal primitive operations whereby the number of machine cycles utilized in the execution of said instruction is reduced when said operand data is ideal with respect to said instruction.

Claim 17

An instruction execution unit responsive to an instruction for processing operand data comprising: (a) determining means for determining from said operand data whether said operand data is ideal with respect to said instruction; (b) primitive operator means for performing a plurality of floating point primitive operations on said operand data including non-ideal primitive operations wherein non-ideal conditions are detected and dealt with; (c) sequencing means, responsive to said instruction, for controlling said primitive operator means to perform sequences of primitive operations to execute said instruction and at least one of said sequences not including non-ideal primitive operations; and (d) selector means, connected to said sequencing means and responsive to said determining means, for selecting said one of said sequences not including non-ideal primitive operations whereby a shorter sequence is executed in the execution of said instruction when said operand data is ideal with respect to said instruction.

Claim 18

An instruction execution unit responsive to an instruction for processing operand data comprising: (a) determining means for determining from said operand data whether said operand data is ideal with respect to said instruction; (b) primitive operator means for performing a plurality of floating point primitive operations on said operand data including non-ideal primitive operations wherein non-ideal conditions are detected and dealt with; (c) sequencing means, responsive to said instruction, for controlling said primitive operator means to perform sequences of primitive operations to execute said instruction and at least one of said sequences not including non-ideal primitive operations; and (d) selector means, connected to said sequencing means and responsive to said determining means, for selecting said one of said sequences not including non-ideal primitive operations whereby a shorter sequence is executed in the execution of said instruction when said operand data is ideal with respect to said instruction.

Claim 19

The unit of claim 14 wherein said primitive operator means performs each primitive operation in a respective machine cycle.

Claim 20

The unit of claim 14 wherein said determining means determines whether said operand data is ideal during the execution of said instruction.

Claim 21

A floating point execution unit, responsive to an instruction for processing operand data, comprising: (a) determining means for determining whether said operand data is ideal with respect to said instruction; (b) execution means for executing a sequence of primitive floating point computations on said operand data to perform said instruction, said primitive floating point computations selected from a set of primitive floating point computations including primitive floating point computations for detecting whether a computation exception condition occurs, said determining means operating prior to or concurrent with the first one of said sequence of primitive floating point computations executed by said execution means with respect to said instruction; and (c) sequencing means, responsive to said determining means, for controlling the sequential selection of primitive floating point computations for execution by said execution means, said sequencing means selecting an alternate sequence of said primitive floating point computations that excludes primitive floating point computations for detecting computation exception conditions to complete the execution of said instruction when said operand data is ideal, whereby fewer primitive floating point computations are required for processing ideal operand data in accordance with said instruction.

Claim 22

A floating point execution unit, responsive to an instruction for processing operand data, comprising: (a) determining means for determining whether said operand data is ideal with respect to said instruction; (b) execution means for executing a sequence of primitive floating point computations on said operand data to perform said instruction, said primitive floating point computations selected from a set of primitive floating point computations including primitive floating point computations for detecting whether a computation exception condition occurs, said determining means operating prior to or concurrent with the first one of said sequence of primitive floating point computations executed by said execution means with respect to said instruction; and (c) sequencing means, responsive to said determining means, for controlling the sequential selection of primitive floating point computations for execution by said execution means, said sequencing means selecting an alternate sequence of said primitive floating point computations that excludes primitive floating point computations for detecting computation exception conditions to complete the execution of said instruction when said operand data is ideal, whereby fewer primitive floating point computations are required for processing ideal operand data in accordance with said instruction.

Claim 23

The execution unit of claim 17 wherein said determining means comprises logic means for testing said operand data to predict the occurrence of exponent underflow, overflow, recomplementing or a zero in the execution of said instruction such that said determining means determines that said operand data is ideal with respect to said instruction based on the predicted nonoccurrence of exponent underflow, overflow, recomplementing or a zero in the execution of said instruction with respect to said operand data.

Claim 24

The floating point execution unit of claim 18 wherein said operand data includes two operands, each of said operands including an operand fraction having a plurality of digits and an operand exponent, and wherein said logic means determines said operand data to be ideal with respect to said instruction by determining: (a) whether said operand fractions are to be added and the one of said operands with the larger magnitude is normalized; (b) whether the one of said operands with the larger magnitude is normalized, said operand exponents are unequal and the one of said operands having the larger exponent has an exponent value of at least `10` Hex; (c) whether the one of said operands with the larger magnitude is normalized, the leading digits of said operand fractions are unequal, and said operand exponent having the larger exponent has an exponent value of at least `10` Hex; (d) whether the operand fractions are to be subtracted; and (e) whether both operand exponents have an exponent value of less than `7F` Hex.

Claim 25

The execution unit of claim 19 wherein said logic means further determines: (a) whether both of said operands are normalized and the sum of said operand exponents is at least `41` Hex; and (b) whether the sum of said operand exponents is less than `CO` Hex.