US4772571A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Process of self aligned nitridation of TiSi2 to form TiN/TiSi2 contact
Assignee: STC PLC
•
Filing: 1987-05-18
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Granted: 1988-09-20
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Expires: 2007-05-18
Abstract
Abstract In order to prevent diffusion of silicon from under a titanium disilicide interconnect (1) and into an overlying aluminium layer (6), the disilicide is selectively nitrided by annealing in nitrogen at the points where interconnection between the disilicide and aluminium is required via holes (4) in a silicon dioxide layer (3). The titanium nitrode contacts (5) thus formed in a truly self-aligned manner provide a good barrier to silicon diffusion while having an acceptable low resistivity.
Inventors
- 👤 Peter D. Scovell
- 👤 Paul J. Rosser
- 👤 Gary J. Tomkins
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 00:46
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/064; H10W20/066; H10W20/40; H10W20/41; H10W20/44; H10W20/4403; H10W20/4437; H10W20/4441; Y; Y10; Y10S; Y10S148/00; Y10S148/019
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
106 words
A method of manufacturing a semiconductor device including the steps of forming a titanium disilicide element on a semiconductor wafer, providing an electrically insulating layer over the wafer, exposing a region of the titanium disilicide element via a hole in the electrically insulating layer, annealing the wafer in nitrogen whereby to form titanium nitride at the exposed titanium disilicide region, metallising the wafer, and patterning the metallisation to form a metal element, the titanium disilicide element being in electrical contact with the metal element via the titanium nitride, which titanium nitride comprises a barrier to the diffusion of silicon from the wafer into the metal element.
Claim 2
Independent Claim
106 words
A method of manufacturing a semiconductor device including the steps of forming a titanium disilicide element on a semiconductor wafer, providing an electrically insulating layer over the wafer, exposing a region of the titanium disilicide element via a hole in the electrically insulating layer, annealing the wafer in nitrogen whereby to form titanium nitride at the exposed titanium disilicide region, metallising the wafer, and patterning the metallisation to form a metal element, the titanium disilicide element being in electrical contact with the metal element via the titanium nitride, which titanium nitride comprises a barrier to the diffusion of silicon from the wafer into the metal element.
Claim 3
Dependent Claim
15 words
A method as claimed in claim 1 wherein the insulating layer is of silicon dioxide.
Claim 4
Dependent Claim
13 words
A method as claimed in claim 1 wherein the metallisation is of aluminium.
Claim 5
Independent Claim
64 words
A method of manufacturing a semiconductor device including the steps of forming a titanium disilicide interconnect on a substrate, annealing a region of the interconnect in nitrogen to form titanium nitride at the region and disposing an aluminium element in electrical contact with the titanium nitride, which titanium nitride comprises a barrier to the diffusion of silicon from the substrate into the aluminium element.
Claim 6
Independent Claim
64 words
A method of manufacturing a semiconductor device including the steps of forming a titanium disilicide interconnect on a substrate, annealing a region of the interconnect in nitrogen to form titanium nitride at the region and disposing an aluminium element in electrical contact with the titanium nitride, which titanium nitride comprises a barrier to the diffusion of silicon from the substrate into the aluminium element.
Claim 7
Dependent Claim
36 words
A method as claimed in claim 1, wherein the titanium nitride-forming annealing step involves pulse heating the wafer to a temperature of 1100° C. in nitrogen for a time of the order of a few seconds.
Claim 8
Dependent Claim
34 words
A method as claimed in claim 1, wherein the titanium nitride-forming annealing step involves heating the wafer to a temperature of 1000° C. in nitrogen for a time of the order of one hour.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-09-20 | 1992-03-21 | 1992-09-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-09-20 | 1996-03-21 | 1996-09-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-09-20 | 2000-03-21 | 2000-09-20 | $7700.00 | Window Closed / Lapsed |