Semiconductor integrated circuit device

Claim 2

A semiconductor integrated circuit device including dynamic memory cells that need to be periodically refreshed, said semiconductor integrated circuit device being adapted to be tested by a test operation performed by means for inspecting predetermined data holding characteristics of said dynamic memory cells, said semiconductor integrated circuit device comprising: a timer circuit which generates output signals for determining a refresh timing of said dynamic memory cells and which comprises a program circuit for changing the period of said output signals in accordance with results regarding said data holding characteristics obtained from said test operation.

Claim 3

A semiconductor integrated circuit device according to claim 1, wherein said program circuit includes a nonvolatile memory element to be programmed in accordance with said results.

Claim 4

A semiconductor integrated circuit device according to claim 2, wherein said nonvolatile memory element is comprised of a fuse element.

Claim 5

A semiconductor integrated circuit device according to claim 1, further comprising an address counter which forms address signals designating one of said dynamic memory cells.

Claim 6

A semiconductor integrated circuit device according to claim 4, wherein said address counter receives said output signals from said timer circuit as incrementing pulses.

Claim 7

A semiconductor integrated circuit device according to claim 5, wherein said program circuit includes a nonvolatile memory element to be programmed in accordance with said results.

Claim 8

A semiconductor integrated circuit device according to claim 6, wherein said nonvolatile memory element is comprised of a fuse element.

Claim 9

A semiconductor integrated circuit device including dynamic memory cells that need to be periodically refreshed, said semiconductor integrated circuit device being adapted to be tested by a test operation performed by means for inspecting predetermined data holding characteristics of said dynamic memory cells, said semiconductor integrated circuit device comprising: a decoder circuit for selecting said dynamic memory cells; an address buffer; and a refresh circuit which comprises: a program circuit which comprises a program element to be programmed in accordance with results regarding said data holding characteristics obtained from said test operation, wherein said program circuit includes means for generating an output signal according to the condition of said program element; a timer circuit coupled to said program circuit for producing output signals whose pulse period varies depending upon said output signal of said program circuit; an address counter which counts the output signals of said timer circuit to form address signals; and means for forming a control signal which controls a multiplexer, wherein said multiplexer is coupled to said refresh circuit for supplying to said decoder circuit the address signal produced either by said address buffer or by said address counter in accordance with said control signal, so that said multiplexer supplies to said decoder circuit the address signal produced by said address counter when the dynamic memory cells specified by said address counter are refreshed.

Claim 10

A semiconductor integrated circuit device including dynamic memory cells that need to be periodically refreshed, said semiconductor integrated circuit device being adapted to be tested by a test operation performed by means for inspecting predetermined data holding characteristics of said dynamic memory cells, said semiconductor integrated circuit device comprising: a decoder circuit for selecting said dynamic memory cells; an address buffer; and a refresh circuit which comprises: a program circuit which comprises a program element to be programmed in accordance with results regarding said data holding characteristics obtained from said test operation, wherein said program circuit includes means for generating an output signal according to the condition of said program element; a timer circuit coupled to said program circuit for producing output signals whose pulse period varies depending upon said output signal of said program circuit; an address counter which counts the output signals of said timer circuit to form address signals; and means for forming a control signal which controls a multiplexer, wherein said multiplexer is coupled to said refresh circuit for supplying to said decoder circuit the address signal produced either by said address buffer or by said address counter in accordance with said control signal, so that said multiplexer supplies to said decoder circuit the address signal produced by said address counter when the dynamic memory cells specified by said address counter are refreshed.

Claim 11

A semiconductor integrated circuit according to claim 8, wherein said program element is comprised of a fuse element.

Claim 12

A semiconductor integrated circuit device including dynamic memory cells that need to be periodically refreshed, said semiconductor integrated circuit device being adapted to be tested by a test operation performed by means for inspecting predetermined data holding characteristics of said dynamic memory cells, said semiconductor integrated circuit device comprising: a memory array including said dynamic memory cells arranged in the form of a matrix; a column decoder circuit for selecting one of memory cell columns in said memory array; an address buffer; and a refresh circuit which comprises: a program circuit which comprises a program element to be programmed in accordance with results regarding said data holding characteristics obtained from said test operation, wherein said program circuit includes means for generating an output signal according to the condition of said program element; a timer circuit coupled to said program circuit for producing output signals whose pulse period varies depending upon said output signal of said program circuit; an address counter which counts the output signals of said timer circuit to form address signals; and means for forming a control signal which controls a multiplexer, wherein said multiplexer is coupled to said refresh circuit for supplying to said column decoder circuit the address signal produced either by said address buffer or by said address counter in accordance with said control signal, so that said multiplexer supplies to said column decoder circuit the address signal produces by said address counter when the dynamic memory cells specified by said address counter are refreshed.

Claim 13

A semiconductor integrated circuit device including dynamic memory cells that need to be periodically refreshed, said semiconductor integrated circuit device being adapted to be tested by a test operation performed by means for inspecting predetermined data holding characteristics of said dynamic memory cells, said semiconductor integrated circuit device comprising: a memory array including said dynamic memory cells arranged in the form of a matrix; a column decoder circuit for selecting one of memory cell columns in said memory array; an address buffer; and a refresh circuit which comprises: a program circuit which comprises a program element to be programmed in accordance with results regarding said data holding characteristics obtained from said test operation, wherein said program circuit includes means for generating an output signal according to the condition of said program element; a timer circuit coupled to said program circuit for producing output signals whose pulse period varies depending upon said output signal of said program circuit; an address counter which counts the output signals of said timer circuit to form address signals; and means for forming a control signal which controls a multiplexer, wherein said multiplexer is coupled to said refresh circuit for supplying to said column decoder circuit the address signal produced either by said address buffer or by said address counter in accordance with said control signal, so that said multiplexer supplies to said column decoder circuit the address signal produces by said address counter when the dynamic memory cells specified by said address counter are refreshed.

Claim 14

A semiconductor integrated circuit device according to claim 10, further comprising a row decoder circuit for selecting one of memory cell rows in said memory array.

Claim 15

A semiconductor integrated circuit device according to claim 11, wherein said program element is comprised of a fuse element.

Claim 16

A semiconductor integrated circuit device according to claim 11, wherein each of said dynamic memory cells includes a selecting MOSFET and a capacitor for storing information data.

Claim 17

A semiconductor integrated circuit device according to claim 8, wherein each of said dynamic memory cells includes a selecting MOSFET and a capacitor for storing information data.

Claim 18

A semiconductor integrated circuit device comprising: dynamic memory cells that need to be periodically refreshed; a latch circuit for storing control data; and a timer circuit which generates output signals for determining a refresh timing of said dynamic memory cells, and which is coupled to said latch circuit so that the period of said output signals varies depending upon the stored control data in said latch circuit.

Claim 19

A semiconductor integrated circuit device comprising: dynamic memory cells that need to be periodically refreshed; a latch circuit for storing control data; and a timer circuit which generates output signals for determining a refresh timing of said dynamic memory cells, and which is coupled to said latch circuit so that the period of said output signals varies depending upon the stored control data in said latch circuit.

Claim 20

A semiconductor integrated circuit device according to claim 15, wherein each of said dynamic memory cells includes a selecting MOSFET and capacitor for storing information data.