US4347589A
Expired / Lapsed
US
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Refresh counter test
Assignee: STMicroelectronics lnc USA
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Filing: 1981-02-17
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Granted: 1982-08-31
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Expires: 2001-02-17
Abstract
Abstract A circuit to permit testing the refresh counter in an integrated circuit memory by writing into cells whose row addresses are determined by the refresh counter.
Inventors
- 👤 Robert J. Proebsting
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 22:25
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/02; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
78 words
In a memory having a refresh counter, row clock generator and column clock generator, a method for testing the operation of the refresh counter comprising: writing a preselected background into the memory; enabling the row clock generator with a refresh signal; selecting a row determined by the refresh counter; enabling the column clock generator; writing in the memory in the row selected by the refresh counter; and reading the memory to determine correct operation of the refresh counter.
Claim 2
Dependent Claim
78 words
In a memory having a refresh counter, row clock generator and column clock generator, a method for testing the operation of the refresh counter comprising: writing a preselected background into the memory; enabling the row clock generator with a refresh signal; selecting a row determined by the refresh counter; enabling the column clock generator; writing in the memory in the row selected by the refresh counter; and reading the memory to determine correct operation of the refresh counter.
Claim 3
Dependent Claim
15 words
The method of claim 1 wherein the column address is determined by the refresh counter.
Claim 4
Dependent Claim
15 words
The method of claim 1 wherein the column address is externally supplied to the memory.
Claim 5
Dependent Claim
137 words
In a memory having a refresh counter, a row clock generator, a column clock generator, a write clock generator, and a row decoder, a circuit for testing the refresh counter comprising: a NAND-gate for receiving refresh and row address strobes and driving the row clock generator; a first NOR-gate for receiving the row address strobe and a write strobe and driving the column clock generator; a second NOR-gate for receiving the row address strobe and a write strobe and driving the write clock generator; a first AND-gate for receiving an external row address and the refresh strobe; an inverter for inverting the refresh strobe; a second AND-gate for receiving the output of the inverter and the refresh counter address; and, an OR-gate for receiving the outputs of the first and second AND-gates and driving the row decoder.
Claim 6
Dependent Claim
137 words
In a memory having a refresh counter, a row clock generator, a column clock generator, a write clock generator, and a row decoder, a circuit for testing the refresh counter comprising: a NAND-gate for receiving refresh and row address strobes and driving the row clock generator; a first NOR-gate for receiving the row address strobe and a write strobe and driving the column clock generator; a second NOR-gate for receiving the row address strobe and a write strobe and driving the write clock generator; a first AND-gate for receiving an external row address and the refresh strobe; an inverter for inverting the refresh strobe; a second AND-gate for receiving the output of the inverter and the refresh counter address; and, an OR-gate for receiving the outputs of the first and second AND-gates and driving the row decoder.
Claim 7
Dependent Claim
24 words
The method of claim 1 wherein the memory further comprises an external row address which is disabled during the testing of the refresh counter.
Claim 8
Independent Claim
114 words
A method of testing the operation of an internal refresh counter in a random access memory having an external address input a refresh signal input and write circuitry, comprising: writing a uniform background into the memory; selecting a row determined by the row address in said internal refresh counter in response to a refresh signal on said refresh signal input; enabling said write circuitry to write one or more bits in said selected row; sequentially repeating said selecting and enabling steps for all of the rows in said random access memory; and sequentially reading each row in said random access memory in response to externally determined row addresses provided on said external address input.
Claim 9
Independent Claim
114 words
A method of testing the operation of an internal refresh counter in a random access memory having an external address input a refresh signal input and write circuitry, comprising: writing a uniform background into the memory; selecting a row determined by the row address in said internal refresh counter in response to a refresh signal on said refresh signal input; enabling said write circuitry to write one or more bits in said selected row; sequentially repeating said selecting and enabling steps for all of the rows in said random access memory; and sequentially reading each row in said random access memory in response to externally determined row addresses provided on said external address input.
References Cited (Backward Citations)
US3737879A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-08-30 | 1986-03-01 | 1986-08-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-08-30 | 1990-03-01 | 1990-08-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-08-30 | 1994-03-01 | 1994-08-31 | $7700.00 | Window Closed / Lapsed |