US4380805A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Tape burn-in circuit
Assignee: STMicroelectronics lnc USA
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Filing: 1980-09-08
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Granted: 1983-04-19
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Expires: 2000-09-08
Abstract
Abstract A circuit for burning-in an integrated circuit memory receives a two state signal at a burn-in terminal (168). A clock refresh signal is provided to a refresh terminal (170) which drives a refresh counter (192). A sequence of addresses are generated by the refresh counter (192) and provided to row decoders (194) and column decoders (196). When the burn-in command provided to the burn-in terminal (168) is at a first state, sense amplifiers (132) within a memory array (107) are disabled so that pullup circuits (148) elevate digit lines (116, 118) to a high voltage level. The high voltage level is transferred into memory cell storage capacitors (120, 122). When the burn-in command is in either the first or the second state, the refresh signal causes a row clock chain generator (176) to generate row clock signals and a column clock chain generator (178) to generate column clock signals. The addresses generated by the refresh counter together with the signals produced by the row and column clock generators cause the memory cells (120), sense amplifier (132) and associated circuitry within the memory array (107) to be burned-in. The memory array (107) can be exercised with signals received through only 4 terminals to make possible concurrent exercising of a plurality of integrated circuits on a tape having no crossovers of conductor lines.
Inventors
- 👤 Robert J. Proebsting
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 09:51
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
243 words
A circuit for burning-in and an integrated semiconductor memory which has a plurality of memory cells that are accessed in response to an address which is provided to row and column decoders, and to row and column clock signals, the memory having a sense amplifier for each of a plurality of digit lines which are connectable to the memory cells, the memory further having pullup circuits for driving digit lines to a high voltage state and a refresh counter responsive to an externally supplied refresh signal for generating addresses for the row and column decoders, the burn-in circuit comprising circuit elements integral with the memory including: a burn-in terminal connected to receive an externally supplied burn-in command having first and second voltage states for burning-in the memory; means connected to said burn-in terminal for disconnecting the sense amplifiers when said burn-in command is at said first state to write a high voltage state into the memory cells by operation of the pullup circuits; means for receiving a repetitive refresh signal to cycle the refresh counter and supply a sequence of row and column addresses to the row and column decoders; means for generating the row clock signals when said burn-in command is at said first state or said second state and the refresh signal is received; and means for generating the column clock signals when said burn-in command is at said first state or said second state and the refresh signal is received.
Claim 2
Dependent Claim
243 words
A circuit for burning-in and an integrated semiconductor memory which has a plurality of memory cells that are accessed in response to an address which is provided to row and column decoders, and to row and column clock signals, the memory having a sense amplifier for each of a plurality of digit lines which are connectable to the memory cells, the memory further having pullup circuits for driving digit lines to a high voltage state and a refresh counter responsive to an externally supplied refresh signal for generating addresses for the row and column decoders, the burn-in circuit comprising circuit elements integral with the memory including: a burn-in terminal connected to receive an externally supplied burn-in command having first and second voltage states for burning-in the memory; means connected to said burn-in terminal for disconnecting the sense amplifiers when said burn-in command is at said first state to write a high voltage state into the memory cells by operation of the pullup circuits; means for receiving a repetitive refresh signal to cycle the refresh counter and supply a sequence of row and column addresses to the row and column decoders; means for generating the row clock signals when said burn-in command is at said first state or said second state and the refresh signal is received; and means for generating the column clock signals when said burn-in command is at said first state or said second state and the refresh signal is received.
Claim 3
Dependent Claim
115 words
The circuit recited in claim 1 wherein said means for generating row clock signals comprises: a first inverter connected to receive the refresh signal; a first NOR gate having a first input connected to receive the burn-in command and a second input connected to receive a row address strobe signal; a second NOR gate connected to receive the output of said first inverter at a first input and connected to receive the output of said first NOR gate at a second input; a second inverter connected to receive the output of the second NOR gate at the input thereof; and means connected to the output of said second inverter for generating the row clock signal.
Claim 4
Dependent Claim
223 words
The circuit recited in claim 1 wherein said means for generating column clock signals comprises: a first inverter connected to receive the refresh signal at the input thereof; a first NOR gate having a first input connected to receive the burn-in command and a second input connected to receive a row address strobe signal; a second NOR gate having a first input connected to receive the output of said first NOR gate and a second input connected to receive the output of said first inverter; a third NOR gate having a first input connected to receive the burn-in command and a second input connected to receive the output of the first NOR gate; a fourth NOR gate connected to receive a column address strobe signal at the first input thereof and connected to receive the output of said third NOR gate at the second input thereof; a fifth NOR gate having the first input connected to receive the burn-in signal and a second input connected to receive the output of said fourth NOR gate; a sixth NOR gate having the first input connected to receive the output of said fifth NOR gate and the second input connected to receive the output of said second NOR gate; and means connected to the output of said sixth NOR gate for generating the column clock signal.
Claim 5
Independent Claim
222 words
A method for burning-in a dynamic semiconductor memory which has a plurality of memory cells that are accessed in response to row and column clock signals, and to an address which is provided to row and column decoders, the memory having a sense amplifier for each of a plurality of digit lines which are connectable to the memory cells, the memory further having pullup circuits for driving digit lines to a high voltage state and a refresh counter responsive to an externally supplied refresh signal for generating addresses for the row and column decoders, comprising the steps of: supplying a burn-in command having first and second voltages states to a burn-in terminal of said memory; disabling said sense amplifier when said burn-in command is at said first state to write a high voltage state into the memory cells by operation of the pullup circuits; applying a repetitive refresh signal to the refresh counter for causing the refresh counter to supply a sequence of row and column addresses to the row and column decoders; generating the row clock signals when said burn-in command is at said first state or said second state and the refresh signal is received; and generating the column clock signals when said burn-in command is at said first state or said second state and the refresh signal is received.
Claim 6
Independent Claim
222 words
A method for burning-in a dynamic semiconductor memory which has a plurality of memory cells that are accessed in response to row and column clock signals, and to an address which is provided to row and column decoders, the memory having a sense amplifier for each of a plurality of digit lines which are connectable to the memory cells, the memory further having pullup circuits for driving digit lines to a high voltage state and a refresh counter responsive to an externally supplied refresh signal for generating addresses for the row and column decoders, comprising the steps of: supplying a burn-in command having first and second voltages states to a burn-in terminal of said memory; disabling said sense amplifier when said burn-in command is at said first state to write a high voltage state into the memory cells by operation of the pullup circuits; applying a repetitive refresh signal to the refresh counter for causing the refresh counter to supply a sequence of row and column addresses to the row and column decoders; generating the row clock signals when said burn-in command is at said first state or said second state and the refresh signal is received; and generating the column clock signals when said burn-in command is at said first state or said second state and the refresh signal is received.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-04-18 | 1986-10-18 | 1987-04-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-04-18 | 1990-10-18 | 1991-04-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-04-18 | 1994-10-18 | 1995-04-19 | $7700.00 | Window Closed / Lapsed |