Patent US4771405A successfully refreshed from Google Patents.
US4771405A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Hidden control bits in a control register
Assignee: NXP USA Inc
•
Filing: 1986-04-14
•
Granted: 1988-09-13
•
Expires: 2006-04-14
Abstract
Abstract First and second unused bits of a multi-bit mapped register are utilized to control a desired function. Each of the bits are capable of assuming first and second stable states. The control function is enabled when the first bit is in the first state and the second bit is in a second state. The function is disabled when the first bit is in the second state and the second bit is in the first state. The function remains unaltered when the first and second bits are each in the same state.
Inventors
- 👤 Kenneth R. Burch
- 👤 Gordon R. Burns
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 15:15
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/18; G11C7/00; G11C7/22
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
189 words
In a data processor having a multi-bit register with at least first and second unused bits each capable of assuming first and second logic states and said register capable of assuming first and second states for use to control a predetermined function, a control circuit comprising: first logic means having inputs coupled to said first and second unused bits of the multi-bit register and having an output for providing a first signal when said first unused bit is in said second logic state and said second unused bit is in said first logic state; second logic means having inputs coupled to said first and second unused bits and having an output for providing a second signal when said first unused bit is in said first logic state and said second unused bit is in said second logic state; and third logic means coupled to the first and second logic means for receiving the first and second signals and providing an output indicating the first and second states of the multi-bit register, wherein said output remains unaltered if said first and second unused bits are in the same logic state.
Claim 2
Dependent Claim
189 words
In a data processor having a multi-bit register with at least first and second unused bits each capable of assuming first and second logic states and said register capable of assuming first and second states for use to control a predetermined function, a control circuit comprising: first logic means having inputs coupled to said first and second unused bits of the multi-bit register and having an output for providing a first signal when said first unused bit is in said second logic state and said second unused bit is in said first logic state; second logic means having inputs coupled to said first and second unused bits and having an output for providing a second signal when said first unused bit is in said first logic state and said second unused bit is in said second logic state; and third logic means coupled to the first and second logic means for receiving the first and second signals and providing an output indicating the first and second states of the multi-bit register, wherein said output remains unaltered if said first and second unused bits are in the same logic state.
Claim 3
Dependent Claim
65 words
A control circuit according to claim 1 wherein said first logic means comprises: a first inverter having an input coupled to said first unused bit and having an output; and a first NAND gate having a first input coupled to the output of said first inverter, having a second input coupled to said second unused bit and having an output coupled to said reset input.
Claim 4
Dependent Claim
69 words
A control circuit according to claim 2 wherein said second logic means comprises: a second inverter having an input coupled to said second unused bit and having an output; and a second NAND gate having a first input coupled to the output of said second inverter and having a second input coupled to said first unused bit, the output of said NAND gate being coupled to said set input.
Claim 5
Dependent Claim
83 words
A control circuit according to claim 3 wherein said third logic means comprises a flip-flop having set and reset inputs and a Q and Q output and comprises: a third NAND gate having a first input coupled to the output of said first NAND gate and having a second input coupled to said Q output; and a fourth NAND gate having a first input coupled to the output of said second NAND gate and having a second input coupled to said Q output.
Claim 6
Dependent Claim
21 words
A control circuit according to claim 4 wherein said third NAND gate has a third input coupled to a reset signal.
Claim 7
Independent Claim
196 words
A method for controlling a function in a data processor in response to first and second states of an unused portion of a multi-bit register, said register having first and second unused bits each capable of assuming first and second logic states, comprising the steps of: providing first logic means having inputs coupled to the first and second unused bits of the multi-bit register, said first logic means providing a first signal when said first unused bit is in said second logic state and said second unused bit is in said first logic state; providing second logic means having inputs coupled to said first and second unused bits of the multi-bit register, said second logic means providing a second signal when said first unused bit is in said first logic state and said second unused bit is in said second logic state; and coupling third logic means to the first and second logic means, said third logic means receiving the first and second signals and providing an output which indicates the first and second states of the multi-bit register and which remains unaltered if the first and second unused bits are in the same logic state.
Claim 8
Independent Claim
196 words
A method for controlling a function in a data processor in response to first and second states of an unused portion of a multi-bit register, said register having first and second unused bits each capable of assuming first and second logic states, comprising the steps of: providing first logic means having inputs coupled to the first and second unused bits of the multi-bit register, said first logic means providing a first signal when said first unused bit is in said second logic state and said second unused bit is in said first logic state; providing second logic means having inputs coupled to said first and second unused bits of the multi-bit register, said second logic means providing a second signal when said first unused bit is in said first logic state and said second unused bit is in said second logic state; and coupling third logic means to the first and second logic means, said third logic means receiving the first and second signals and providing an output which indicates the first and second states of the multi-bit register and which remains unaltered if the first and second unused bits are in the same logic state.
Claim 9
Dependent Claim
148 words
In a data processor having a multi-bit register with first and second unused bits each capable of assuming first and second logic states, said register capable of assuming first and second states, a method for controlling a predetermined function in the data processor with the first and second unused bits, comprising the steps of: providing a first signal in response to the first unused bit assuming the second logic state and the second unused bit assuming the first logic state; providing a second signal in response to the first unused bit assuming the first logic state and the second unused bit assuming the second logic state; and providing a third signal in response to the first and second signals, said third signal indicating the first and second states of the multi-bit register and remaining unaltered if the first and second unused bits are in the same logic state.
Claim 10
Dependent Claim
148 words
In a data processor having a multi-bit register with first and second unused bits each capable of assuming first and second logic states, said register capable of assuming first and second states, a method for controlling a predetermined function in the data processor with the first and second unused bits, comprising the steps of: providing a first signal in response to the first unused bit assuming the second logic state and the second unused bit assuming the first logic state; providing a second signal in response to the first unused bit assuming the first logic state and the second unused bit assuming the second logic state; and providing a third signal in response to the first and second signals, said third signal indicating the first and second states of the multi-bit register and remaining unaltered if the first and second unused bits are in the same logic state.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-09-13 | 1992-03-14 | 1992-09-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-09-13 | 1996-03-14 | 1996-09-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-09-13 | 2000-03-14 | 2000-09-13 | $7700.00 | Window Closed / Lapsed |