Multiplexed bus data encoder and decoder for facilitating data recording

Claim 2

A circuit for encoding a digital signal comprising multiple words on a bus, said digital signal coded in a first bit format at a first data rate, each word including a synchronization portion coded in a bit format invalid in said first bit format, a data portion, and a parity portion, and at least one gap portion between said multiple words, said circuit comprising: encoder means for converting a selected portion said digital signal into a synthesized digital signal coded in a second bit format at a second data rate, said second data rate being asynchronous to said first data rate, said selected portion not including said synchronization portion, said first data rate being greater than said second data rate; synthesis means for synthesizing a new synchronization portion of said synthesized digital signal from said synchronization portion of said digital signal according to a predetermined protocol, and for inserting data in said predetermined protocol in said gap, said new synchronization portion being written into and across said gap, said synthesis means coupled to said encoder means; and means for recording said synthesized digital signal on a single track of magnetic tape at said lower second data rate, said means for recording coupled to said encoder means and synthesis means, whereby said data originally generated at said higher first data rate is synthesized to include said invalid synchronization portion in a format characterized by a reduced second data rate so that said means for recording said synthesized digital signal has a substantially lower frequency capability corresponding to said second data rate.

Claim 3

The circuit of claim 1 further comprising: decoder means for converting said digital signal in said second bit format of reduced second data rate into said first bit format of said higher originating first data rate; and resynthesis means coupled to said decoder means for resynthesizing said synchronization portion in said invalid bit format, said decoder means being coupled to said means for recording, whereby data at said original higher first data rate may be recorded by said means for recording and reconverted into said original format so that processing of recorded data is independent of said means for recording said data.

Claim 4

The circuit of claim 2 wherein said resynthesis means comprises: means for recognizing said synthesized synchronization portion; and means for resynthesizing said synchronization portion in said invalid bit format at said higher first data rate, said means for resynthesizing said invalid synchronization portion being coupled to said means for recognizing.

Claim 5

The circuit of claim 3 wherein said resynthesizing means resynthesizes said synchronization portion by shifting logic transitions within said synchronization portion back to said original first bit format.

Claim 6

The circuit of claim 2 wherein said resynthesizing means resynthesizes said synchronization portion by shifting logic transitions within said synchronization prefix back to said original first bit format.

Claim 7

The circuit of claim 1 wherein said synthesis means comprises: means for recognizing a synchronization portion; means for synthesizing a new synchronization portion in said second bit format corresponding to said invalid synchronization portion, said means for synthesizing coupled to said means for recognizing said synchronization portion and being responsive to said means for recognizing, said means for synthesizing synthesizing said new synchronization portion in said second bit format.

Claim 8

The circuit of claim 6 wherein said synthesis means generates a new synchronization portion in said new second bit format according to a predetermined shift the timing of transition of logic levels within said synchronization portion inserted according to said predetermined protocol in said gap, said new synchronization portion being written into said gap.

Claim 9

The circuit of claim 1 wherein said synthesis means generates a new synchronization portion in said new second bit format according to a predetermined shift in the timing of transition of logic levels within said synchronization portion inserted according to said predetermined protocol in said gap, said new synchronization portion being written into said gap.

Claim 10

A circuit for encoding a digital signal on a bus coded in a first format at a first data rate, said digital signal being coded according to said first format and including a synchronization portion coded in a format invalid in said first format, said circuit comprising: encoder means for converting a selected portion said digital signal into a synthesized digtal signal coded in a second format at a second data rate, said selected portion not including said synchronization portion, said first data rate being greater than said second data rate; synthesis means for synthesizing a new synchronization portion of said synthesized digital signal from said synchronization portion of said digital signal according to a predetermined protocol, said synthesis means coupled to said encoder means; and means for recording said synthesized digital signal, said means for recording coupled to said decoder means and synthesis means, wherein said encoder means comprises: a first encoder for converting signals in a Manchester coded format on a 1553 MUX bus into NRZ-L formatted signals; and a second encoder coupled to said first encoder, said second encoder for converting said NRZ-L formatted data into DM-M formatted data run at said reduced second data rate as compared to said first data rate of said Manchester and NRZ-L formatted signals, whereby said data originally generated at said higher first data rate is synthesized to include said invalid synchronization portion in a format characterized by a reduced second data rate so that said means for recording said synthesized digital signal has a substantially lower frequency capability corresponding to said second data rate.

Claim 11

A circuit for encoding a digital signal on a bus coded in a first format at a first data rate, said digital signal being coded according to said first format and including a synchronization portion coded in a format invalid in said first format, said circuit comprising: encoder means for converting a selected portion said digital signal into a synthesized digtal signal coded in a second format at a second data rate, said selected portion not including said synchronization portion, said first data rate being greater than said second data rate; synthesis means for synthesizing a new synchronization portion of said synthesized digital signal from said synchronization portion of said digital signal according to a predetermined protocol, said synthesis means coupled to said encoder means; and means for recording said synthesized digital signal, said means for recording coupled to said decoder means and synthesis means, wherein said encoder means comprises: a first encoder for converting signals in a Manchester coded format on a 1553 MUX bus into NRZ-L formatted signals; and a second encoder coupled to said first encoder, said second encoder for converting said NRZ-L formatted data into DM-M formatted data run at said reduced second data rate as compared to said first data rate of said Manchester and NRZ-L formatted signals, whereby said data originally generated at said higher first data rate is synthesized to include said invalid synchronization portion in a format characterized by a reduced second data rate so that said means for recording said synthesized digital signal has a substantially lower frequency capability corresponding to said second data rate.

Claim 12

The circuit of claim 9 wherein said synthesis means comprises: means for recognizing a synchronization portion; means for synthesizing a new synchronization portion in said second coded format corresponding to said invalid synchronization portion, said means for synthesizing coupled to said means for recognizing said synchronization portion and being responsive to said means for recognizing to synthesize said new synchronization portion in said second coded format.

Claim 13

The circuit of claim 10 wherein said synthesis means generates a new synchronization portion in said new second bit format according to a predetermined shift in the timing of transition of logic levels within said synchronization prefix inserted according to said predetermined protocol in said gap, said new synchronization portion being written into said gap.

Claim 14

A circuit for encoding a digital signal on a bus coded in a first format at a first data rate, said digital signal being coded according to said first format and including a synchronization portion coded in a format invalid in said first format, said circuit comprising: encoder means for converting a selected portion said signal into a synthesized digital signal coded in a second format at a second data rate, said selected portion not including said synchronization portion, said first data rate being greater than said second data rate; synthesis means for synthesizing a new synchronization portion of said synthesized digital signal from said synchronization portion of said digital signal according to a predetermined protocol, said synthesis means coupled to said encoder means; and means for recording said synthesized digital signal, said means for recording coupled to said decoder means and synthesis means, decoder means for converting said digital signal in said second format of reduced second data rate into said first format of said higher originating first data rate; and resynthesis means coupled to said decoder means for resynthesizing said synchronization portion in said invalid format, said decoder means being coupled to said means for recording, wherein said decoder means comprises: a first decoder for reconverting said digital signal from DM-M code format at said second data rate into NRZ-L format at said first data rate; and a second decoder for reconverting said NRZ-L format digital data into said Manchester coded data at said first data rate, whereby said data originally generated at said higher first data rate is synthesized to include invalid synchronization portion in a format characterized by a reduced second data rate so that said means for recording said synthesized digital signal has a substantially lower frequency capability corresponding to said second data rate and whereby data at said original higher first data rate may be recorded by said means for recording and reconverted into said original format so that processing of said data appears to be independent of said means for recording said data.

Claim 15

A circuit for encoding a digital signal on a bus coded in a first format at a first data rate, said digital signal being coded according to said first format and including a synchronization portion coded in a format invalid in said first format, said circuit comprising: encoder means for converting a selected portion said signal into a synthesized digital signal coded in a second format at a second data rate, said selected portion not including said synchronization portion, said first data rate being greater than said second data rate; synthesis means for synthesizing a new synchronization portion of said synthesized digital signal from said synchronization portion of said digital signal according to a predetermined protocol, said synthesis means coupled to said encoder means; and means for recording said synthesized digital signal, said means for recording coupled to said decoder means and synthesis means, decoder means for converting said digital signal in said second format of reduced second data rate into said first format of said higher originating first data rate; and resynthesis means coupled to said decoder means for resynthesizing said synchronization portion in said invalid format, said decoder means being coupled to said means for recording, wherein said decoder means comprises: a first decoder for reconverting said digital signal from DM-M code format at said second data rate into NRZ-L format at said first data rate; and a second decoder for reconverting said NRZ-L format digital data into said Manchester coded data at said first data rate, whereby said data originally generated at said higher first data rate is synthesized to include invalid synchronization portion in a format characterized by a reduced second data rate so that said means for recording said synthesized digital signal has a substantially lower frequency capability corresponding to said second data rate and whereby data at said original higher first data rate may be recorded by said means for recording and reconverted into said original format so that processing of said data appears to be independent of said means for recording said data.

Claim 16

The circuit of claim 12 wherein said resynthesis means comprises: means for recognizing said synthesized synchronization portion; and means for resynthesizing said synchronization portion in said invalid code format at said higher first clock rate, said means for resynthesizing said invalid synchronization potion being coupled to said means for recognizing.

Claim 17

The circuit of claim 13 wherein said resynthesizing means resynthesizes said synchronization portion by shifting logic transitions within said synchronization portion back to said original first coded format.

Claim 18

A circuit for encoding a digital signal on a bus coded in a first format at a first data rate, said digital signal being coded according to said first format and including a synchronization portion coded in a format invalid in said first format, said circuit comprising: encoder means for converting a selected portion said digital signal into a synthesized digital signal coded in a second format at a second data rate, said selected portion not including said synchronization portion, said first data rate being greater than said second data rate; synthesis means for synthesizing a new synchronization portion of said synthesized digital signal from said synchronization portion of said digital signal according to a predetermined protocol, said synthesis means coupled to said encoder means; and means for recording said synthesized digital signal, said means for recording coupled to said decoder means and synthesis means, wherein said synthesis means comprises: means for recognizing a synchronization portion; means for synthesizing a new synchronization portion in said second coded format corresponding to said invalid synchronization portion, said means for synthesizing coupled to said means for recognizing said synchronization portion and being responsive to said means for recognizing to synthesize said new synchronization portion in said second coded format, wherein said means for recognizing said synchronization portion comprises a flip-flop coupled to said encoder means, said flip-flop assuming a first logic state upon receipt of a signal representative of a command synchronization portion and assuming a second logic state upon receiving a signal representative of a data synchronization portion; and wherein said means for synthesizing said new synchronization portion comprises an output register coupled to said encoder means wherein said new format digital word is stored within said register and wherein a selected portion of said register is reserved for said new synchronization portion, said selected portion of said register being coupled to said output of said flip-flop in a predetermined mapping between said selected bit portions of said register and said outputs of said flip-flop, whereby said data originally generated at said higher first data rate is synthesized to include said invalid synchronization portion in a format characterized by a reduced second data rate so that said means for recording said synthesized digital signal has a substantially lower frequency capability corresponding to said second data rate.

Claim 19

A circuit for encoding a digital signal on a bus coded in a first format at a first data rate, said digital signal being coded according to said first format and including a synchronization portion coded in a format invalid in said first format, said circuit comprising: encoder means for converting a selected portion said digital signal into a synthesized digital signal coded in a second format at a second data rate, said selected portion not including said synchronization portion, said first data rate being greater than said second data rate; synthesis means for synthesizing a new synchronization portion of said synthesized digital signal from said synchronization portion of said digital signal according to a predetermined protocol, said synthesis means coupled to said encoder means; and means for recording said synthesized digital signal, said means for recording coupled to said decoder means and synthesis means, wherein said synthesis means comprises: means for recognizing a synchronization portion; means for synthesizing a new synchronization portion in said second coded format corresponding to said invalid synchronization portion, said means for synthesizing coupled to said means for recognizing said synchronization portion and being responsive to said means for recognizing to synthesize said new synchronization portion in said second coded format, wherein said means for recognizing said synchronization portion comprises a flip-flop coupled to said encoder means, said flip-flop assuming a first logic state upon receipt of a signal representative of a command synchronization portion and assuming a second logic state upon receiving a signal representative of a data synchronization portion; and wherein said means for synthesizing said new synchronization portion comprises an output register coupled to said encoder means wherein said new format digital word is stored within said register and wherein a selected portion of said register is reserved for said new synchronization portion, said selected portion of said register being coupled to said output of said flip-flop in a predetermined mapping between said selected bit portions of said register and said outputs of said flip-flop, whereby said data originally generated at said higher first data rate is synthesized to include said invalid synchronization portion in a format characterized by a reduced second data rate so that said means for recording said synthesized digital signal has a substantially lower frequency capability corresponding to said second data rate.

Claim 20

A circuit for encoding a digital signal on a bus coded in a first format at a first data rate, said digital signal being coded according to said first format and including a synchronization portion coded in a format invalid in said first format, said circuit comprising: encoder means for converting a selected portion said digital signal into a synthesized digital signal coded in a second format at a second data rate, said selected portion not including said synchronization portion, said first data rate being greater than said second data rate; synthesis means for synthesizing a new synchronization portion of said synthesized digital signal from said synchronization portion of said digital signal according to a predetermined protocol, said synthesis means coupled to said encoder means; and means for recording said synthesized digital signal, said means for recording coupled to said decoder means and synthesis means, decoder means for converting said digital signal in said second format of reduced second data rate into said first format of said higher originating first data rate; and resynthesis means coupled to said decoder means for resynthesizing said synchronization portion in said invalid format, said decoder means being coupled to said means for recording, wherein said resynthesis means comprises: means for recognizing said synthesized synchronization portion; and means for resynthesizing said synchronization portion in said invalid code format at said higher first data rate, said means for resynthesizing said invalid synchronization portion being coupled to said means for recognizing, wherein said means for recognizing said synthesized synchronization portion comprises a register and a plurality of logic gates coupled to selected bit outputs of said register, said synthesized synchronization portion having a predetermined logic pattern, said plurality of logic gates generating an output signal in response to the occurrence of said predetermined logic pattern on said selected ones of bit outputs of said register; and wherein said means for resynthesizing said invalid synchronization portion comprises a register having a plurality of bit input terminals, each bit input terminal corresponding to a predetermined fraction of a data bit interval, selected ones of said bit input terminals being provided with corresponding logic levels from said new synchronization portion according to an inverse of said predetermined logic pattern, whereby said data originally generated at said higher first data rate is synthesized to include said invalid synchronization portion in a format characterized by a reduced second data rate so that said means for recording said synthesized digital signal has a substantially lower frequency capability corresponding to said second data rate, and whereby data at said original higher first data rate may be recorded by said means for recording and reconverted into said original format so that processing of said data appears to be independent of said means for recording said data.

Claim 21

A circuit for encoding a digital signal on a bus coded in a first format at a first data rate, said digital signal being coded according to said first format and including a synchronization portion coded in a format invalid in said first format, said circuit comprising: encoder means for converting a selected portion said digital signal into a synthesized digital signal coded in a second format at a second data rate, said selected portion not including said synchronization portion, said first data rate being greater than said second data rate; synthesis means for synthesizing a new synchronization portion of said synthesized digital signal from said synchronization portion of said digital signal according to a predetermined protocol, said synthesis means coupled to said encoder means; and means for recording said synthesized digital signal, said means for recording coupled to said decoder means and synthesis means, decoder means for converting said digital signal in said second format of reduced second data rate into said first format of said higher originating first data rate; and resynthesis means coupled to said decoder means for resynthesizing said synchronization portion in said invalid format, said decoder means being coupled to said means for recording, wherein said resynthesis means comprises: means for recognizing said synthesized synchronization portion; and means for resynthesizing said synchronization portion in said invalid code format at said higher first data rate, said means for resynthesizing said invalid synchronization portion being coupled to said means for recognizing, wherein said means for recognizing said synthesized synchronization portion comprises a register and a plurality of logic gates coupled to selected bit outputs of said register, said synthesized synchronization portion having a predetermined logic pattern, said plurality of logic gates generating an output signal in response to the occurrence of said predetermined logic pattern on said selected ones of bit outputs of said register; and wherein said means for resynthesizing said invalid synchronization portion comprises a register having a plurality of bit input terminals, each bit input terminal corresponding to a predetermined fraction of a data bit interval, selected ones of said bit input terminals being provided with corresponding logic levels from said new synchronization portion according to an inverse of said predetermined logic pattern, whereby said data originally generated at said higher first data rate is synthesized to include said invalid synchronization portion in a format characterized by a reduced second data rate so that said means for recording said synthesized digital signal has a substantially lower frequency capability corresponding to said second data rate, and whereby data at said original higher first data rate may be recorded by said means for recording and reconverted into said original format so that processing of said data appears to be independent of said means for recording said data.