Split-phase adaptive decoding electronics

Claim 2

A decoder circuit for digital data comprising: a first clocked delay circuit with a plurality of tandem delay stages for receiving and delaying a continuous split-phase signal representing a first binary value by signal transitions at the bit cell boundaries and representing another binary value by signal transitions at the bit cell boundaries plus an additional midbit signal transition; a source of shift pulses connected to said clocked delay circuit, said source adapted to emit a plurality of output signals occuring during each bit cell duration, said plurality of signals being substantially equal to the number of tandem delay stages whereby the split-phase signal applied to said clocked delay circuit is delayed on bit cell duration, or a whole number multiple thereof; decoding means connected to receive said split-phase signal and also connected to receive the delayed split-phase signal from said delay circuit and operative in response to a comparison between the two signals for emitting a decoded output signal having one data level representative of a first binary value during the duration that the compared signals are identical and for emitting the other data level representative of another binary value during the duration that the compared signals are opposite; and a feedback control loop operating on the said decoded output signal to adjust the frequency of said shift pulses to vary the delay of said first clocked delay circuit.

Claim 3

A decoder circuit in accordance with claim 1 wherein the continuous split-phase includes signal transition shifts from their assigned bit cell locations due to random circuit disturbances, and wherein said decoding means emits noise slivers along with the decoded data level, said noise slivers being emitted at substantially a midbit location in response to the transition shifts; said decoding means further comprising: means connected to the output of said decoding means for removing said noise slivers from said decoded binary signals.

Claim 4

A decoder circuit in accordance with claim 2 wherein said means for removing said noise slivers comprises a digital filter.

Claim 5

A decoder circuit in accordance with claim 3 wherein said digital filter comprises: a multistage shift register having a plurality of stages connected in tandem; means connecting the stages of said shift register to said source of shift pulses; and signal summing means connected in common to said plurality of register stages for summing the signals shifted through said register stages.

Claim 6

A decoder circuit in accordance with claim 4 wherein said summing means yields a substantially regularly stepped triangular wave having said noise slivers present in the waveform as step discrepancies located essentially at a predetermined signal threshold in said stepped triangular wave; said decoder further comprising a limiter circuit connected to the output of said summing means for emitting a first digital level in response to a portion of said stepped triangular wave less than said predetermined signal threshold, and a second digital level in response to the portion of said stepped triangular wave in excess of said predetermined signal threshold.

Claim 7

A decoder circuit in accordance with claim 5 wherein: said limiter circuit emits short-duration level shifts representative of the noise slivers and reordered to the leading and trailing edge boundaries of the signal emitted by the limiter.

Claim 8

A decoder circuit in accordance with claim 6 and further comprising: a bistable device connected to the output of said limiter circuit for emitting output levels free of the reordered noise slivers.

Claim 9

A decoder circuit in accordance with claim 7 and further comprising: a clock circuit for deriving a clock signal from selected transitions in said split-phase signal; and means applying said clock signal to said bistable device.

Claim 10

A decoder circuit in accordance with claim 8 wherein said derived clock cirCuit comprises: means for selecting said transitions from said split-phase signal aligned at substantially the midbit location of signals emitted from said limiter circuit.

Claim 11

A decoder circuit in accordance with claim 9 wherein said selecting means of said derived clock circuit comprises: first deriving means for emitting a first series of pulses derived from a first direction transition in said continuous split-phase signal; second deriving means for emitting a second series of pulses derived from a second direction transition in said continuous split-phase signal; gating means connected to the output of said first and second deriving means, and means connecting said gating means to said limiter circuit for selectively inhibiting or enabling said gating means.

Claim 12

A decoder circuit in accordance with claim 8 wherein: said digital filter represents an additional delay to the decoded binary values, and said decoder circuit further comprises: an additional clocked delay circuit having an input and an output respectively connected between said first clocked delay circuit and said clock circuit, said additional delay circuit having a delay time selected to compensate for the time delay introduced by said digital filter; and means applying shift pulses from said source to said additional clocked delay circuit.

Claim 13

A decoder circuit in accordance with claim 11 wherein said digital filter comprises: a lesser number of stages than the number of stages in said first clocked delay, and said additional clocked delay circuit comprises a number of tandem-connected stages equal to the number of stages in said digital filter.

Claim 14

A decoder circuit in accordance with claim 1 wherein said split-phase signal is received from a magnetic medium, said medium and said decoder tending to introduce signal disturbances which vary the signal transitions to less or more than their assigned bit cell locations, and said feedback control loop further comprises: means for varying the delay time of said first clocked delay circuit to match the variations in said transitions.

Claim 15

A decoder circuit in accordance with claim 13 wherein said delay time varying means comprises: said source of shift pulses; and means for varying the frequency of shift pulses from said shift pulse source during each bit cell duration.

Claim 16

A decoder circuit in accordance with claim 13 wherein said bit cell duration is assigned in accordance with a bit rate of said binary value represented by said split-phase signal, and an initially selected frequency of shift pulses emitted by said source is substantially equal to the number of tandem delay stages in said clocked delay circuit times the bit rate, whereby each binary value representing portion of said split-phase signal is delayed one bit cell time by said clocked delay circuit.

Claim 17

A decoder circuit in accordance with claim 15 wherein said time delay varying means comprises: means for varying the output frequency of said source to more or less than the initially selected frequency.

Claim 18

A decoder circuit in accordance with claim 16 wherein said means for varying the output frequency further comprises: a frequency-locked feedback loop connected to said source and adapted to control the frequency output thereof in accordance with the repetition rate of signals outputted from said decoding means.

Claim 19

A decoder circuit in accordance with claim 17 and further comprising: means for emitting a clock signal for each binary value emitted from said decoding means, and means applying said clock signal to said frequency-locked feedback loop.

Claim 20

A decoder circuit in accordance with claim 18 wherein said source of shift pulses comprises: a signal-controlled variable oscillator circuit; and said frequency-locked feedback loop comprises control signal emitting means connected to said variable oscillator.

Claim 21

A decoder circuit in accordance with claim 19 wherein said frEquency-locked feedback loop comprises: means dividing the number of pulses emitted from said oscillator circuit by a number equal to the number of tandem delay stages for emitting one pulse each for said number of pulses; and wherein said control signal emitting means comprises: means comparing the output of said dividing means with the output of said clock circuit for emitting first or second control signals to increase or decrease the output frequency of said oscillator circuit.

Claim 22

A decoder circuit for emitting digital data having a predetermined bit rate with data appearing during assigned bit cell intervals in which bits of one type are represented by a first level signal and bits of a second type are represented by a second level signal said circuit comprising: means for receiving a continuous bilevel signal having guaranteed level transitions at each bit cell boundary with bits of one type represented by an additional midbit level transition and bits of another type represented by the lack of an additional midbit transition such that a one-bit delayed version of the signal is adapted for comparison with itself during decoding to yield the original discrete data signal levels; a multistage shift register connected to said signal receiving means; an oscillator having an output frequency which is a multiple of the bit rate, said multiple being substantially the same as the number of stages in said shift register for providing a one-bit cell delay time to said continuous signal; signal comparing means connected to receive said delayed signal and said continuous bilevel signal in nondelayed form and operative free of any clocking signal for emitting a decoded output signal having a first level when the compared signals are the same and having a second level when the compared signals are different; and a feedback control loop operating on said decoded output signal to adjust the frequency of the oscillator output to said multistage shift register to vary the delay time of the continuous signal through said shift register.

Claim 23

A decoder circuit for emitting digital data having a predetermined bit rate with data appearing during assigned bit cell intervals in which bits of one type are represented by a first level signal and bits of a second type are represented by a second level signal said circuit comprising: means for receiving a continuous bilevel signal having guaranteed level transitions at each bit cell boundary with bits of one type represented by an additional midbit level transition and bits of another type represented by the lack of an additional midbit transition such that a one-bit delayed version of the signal is adapted for comparison with itself during decoding to yield the original discrete data signal levels; a multistage shift register connected to said signal receiving means; an oscillator having an output frequency which is a multiple of the bit rate, said multiple being substantially the same as the number of stages in said shift register for providing a one-bit cell delay time to said continuous signal; signal comparing means connected to receive said delayed signal and said continuous bilevel signal in nondelayed form and operative free of any clocking signal for emitting a decoded output signal having a first level when the compared signals are the same and having a second level when the compared signals are different; and a feedback control loop operating on said decoded output signal to adjust the frequency of the oscillator output to said multistage shift register to vary the delay time of the continuous signal through said shift register.

Claim 24

Decoder apparatus in accordance with claim 21 wherein: said signal comparing means continually emits one level for one bit type during a bit cell interval that the compared signals are the same, and continually emits another level for the other bit type during a bit cell interval that the compared signals are different.

Claim 25

A decoder circuit in accordance with claim 22 wherein the continuous signal includes shifts in the level transitions from their assigned bit cell locations due to random circuit disturbances, and wherein said signal comparing means emits noise slivers at substantially a midbit location of said emitted levels in response to the transition shifts; said decoding means further comprising: means for removing said noise slivers comprising a digital aperture filter.

Claim 26

A decoder circuit in accordance with claim 23 wherein said digital aperture filter comprises: an additional multistage shift register having a plurality of stages connected in tandem: means connecting the stages of said additional shift register to said oscillator for shifting said noise containing signal through the stages of said additional shift register; and signal summing means connected in common to said plurality of register stages for summing the signals shifted through said register stages, whereby the summation yields said decoded data levels free of slivers over substantially a full bit cell interval.

Claim 27

A decoder circuit for digital data comprising: a first clocked delay circuit with a plurality of tandem delay stages for receiving and delaying a continuous split-phase signal representing a first binary value by signal transitions at the bit cell boundaries and representing another binary value by signal transitions at the bit cell boundaries plus and additional midbit signal transition; said continuous split-phase signal further including signal transition shifts from their assigned bit cell locations due to random circuit disturbances; a source of shift pulses connected to said first clocked delay circuit, said source adapted to emit a plurality of output signals occurring during each bit cell duration, said plurality of signals being substantially equal to the number of tandem delay stages whereby the split-phase signal applied to said clocked delay circuit is delayed one bit cell duration, or a whole number multiple thereof; decoding means connected to receive said split-phase signal and also connected to receive the delayed split-phase signal from said delay circuit and operative in response to a comparison between the two signals for emitting one data signal level representative of a first binary value during the duration that the compared signals are identical and for emitting the other data signal level representative of another binary value during the duration that the compared signals are opposite, said decoding means characterized in that it emits noise slivers along with the decoded data signal levels, said noise slivers being emitted at substantially a midbit location in response to the transition shifts in said continuous split-phase signal; said decoder circuit further comprising: digital filter means connected to the output of said decoding means for removing said noise slivers from said decoded binary signals, said digital filter means comprising: a multistage shift register having a plurality of stages connected in tandem; means connecting the stages of said shift register to said source of shift pulses; and signal summing means connected in common to said plurality of register stages for summing the signals shifted through said register stages.

Claim 28

A decoder circuit for digital data comprising: a first clocked delay circuit with a plurality of tandem delay stages for receiving and delaying a continuous split-phase signal representing a first binary value by signal transitions at the bit cell boundaries and representing another binary value by signal transitions at the bit cell boundaries plus and additional midbit signal transition; said continuous split-phase signal further including signal transition shifts from their assigned bit cell locations due to random circuit disturbances; a source of shift pulses connected to said first clocked delay circuit, said source adapted to emit a plurality of output signals occurring during each bit cell duration, said plurality of signals being substantially equal to the number of tandem delay stages whereby the split-phase signal applied to said clocked delay circuit is delayed one bit cell duration, or a whole number multiple thereof; decoding means connected to receive said split-phase signal and also connected to receive the delayed split-phase signal from said delay circuit and operative in response to a comparison between the two signals for emitting one data signal level representative of a first binary value during the duration that the compared signals are identical and for emitting the other data signal level representative of another binary value during the duration that the compared signals are opposite, said decoding means characterized in that it emits noise slivers along with the decoded data signal levels, said noise slivers being emitted at substantially a midbit location in response to the transition shifts in said continuous split-phase signal; said decoder circuit further comprising: digital filter means connected to the output of said decoding means for removing said noise slivers from said decoded binary signals, said digital filter means comprising: a multistage shift register having a plurality of stages connected in tandem; means connecting the stages of said shift register to said source of shift pulses; and signal summing means connected in common to said plurality of register stages for summing the signals shifted through said register stages.

Claim 29

A decoder circuit in accordance with claim 25 wherein said summing means yields a substantially regularly stepped triangular wave having said noise slivers present in the waveform as step discrepancies located essentially at a predetermined signal threshold in said stepped triangular wave; said decoder further comprising a limiter circuit connected to the output of said summing means for emitting a first digital level in response to a portion of said stepped triangular wave less than said predetermined signal threshold, and a second digital level in response to the portion of said stepped triangular wave in excess of said predetermined signal threshold.

Claim 30

A decoder circuit in accordance with claim 25 wherein: said limiter circuit emits short-duration level shifts representative of the noise slivers and reordered to the leading and trailing edge boundaries of the signal emitted by the limiter.

Claim 31

A decoder circuit in accordance with claim 25 and further comprising: a bistable device connected to the output of said limiter circuit for emitting output levels free of the reordered noise slivers.

Claim 32

A decoder circuit in accordance with claim 25 and further comprising: a clock circuit for deriving a clock signal from selected transitions in said split-phase signal; and means applying said clock signal to said bistable device.

Claim 33

A decoder circuit in accordance with claim 25 wherein said derived clock circuit comprises: means for selecting said transitions from said split-phase signal aligned at substantially the midbit location of signals emitted from said limiter circuit.

Claim 34

A decoder circuit in accordance with claim 25 wherein said selecting means of said derived clock circuit comprises: first deriving means for emitting a first series of pulses derived from a first direction transition in said continuous split-phase signal; second deriving means for emitting a second series of pulses derived from a second direction transition in said continuous split-phase signal; gating means connected to the output of said first and second deriving means; and means connecting said gating means to said limiter circuit for selectively inhibiting or enabling said gating means.

Claim 35

A decoder circuit in accordance with claim 25 wherein: said digital filter represents an additional delay to the decoded binary values, and said decoder circuit further comprises: an additional clocked delay circuit having an input and an output respectively connected between said first clocked delay circuit and said clock circuit, said additional delay circuit having a delay time selected to compensate for the time delay introduced by said digital filter; and means applying shift pulses from said source to said additional clocked delay circuit.