US3705398A
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Digital format converter
Assignee: Iteris Inc
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Filing: 1970-08-11
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Granted: 1972-12-05
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Expires: 1990-08-11
Abstract
Abstract Apparatus for converting serial digital data which is phase encoded in accordance with any bi-phase or double density format to its NRZ format equivalent accompanied by a coherent clock signal. The input data and a train of clock pulses are applied to a data synchronizer which generates a first pulse for each leading and trailing edge transition of the input data in synchronism with the clock pulses. A ring counter driven by the clock pulses generates a series of second pulses in accordance with a predetermined time sequence, the first pulses being applied to the ring counter to restart the time sequence, whereby the output of the ring counter is indicative of the absence of a transition of the input data for a predetermined time period. The first and second pulses are applied to a flip-flop which changes state upon the occurrence of a first or a second pulse, the output of the flip-flop comprising a coherent clock signal. The first and second pulses and the clock signal are applied to logic circuitry which generates the NRZ format equivalent of the input data for all bi-phase and double density formats.
Inventors
- 👤 Ronald F Kostenbauer
- 👤 James P Welch
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 06:33
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/38; H04L25/40; H04L25/49; H04L25/4904; G; G11; G11B; G11B20/00; G11B20/10; G11B20/14; G11B20/1403; G11B20/1407; G11B20/1419; G11B20/1423
Claims Analysis
Total Claims: 29
Claim 1
Independent Claim
147 words
Apparatus for converting serial digital data, phase encoded in accordance with a self-clocking format, to its NRZ format equivalent and a coherent clock signal, comprising: input means responsive to said data for generating a first pulse for each transition of said data; generator means for generating a series of second pulses in accordance with a predetermined time sequence, said time sequence being determinable independently of the period of said data, said first pulses being applied to said generator means for restarting said time sequence; means responsive to said first and second pulses for generating said coherent clock signal, said clock signal comprising a wave which changes state upon the occurence of a first or a second pulse; and logic means responsive to said first and second pulses and said clock signal for generating said NRZ format equivalent of said digital data in synchronism with said clock signal.
Claim 2
Dependent Claim
147 words
Apparatus for converting serial digital data, phase encoded in accordance with a self-clocking format, to its NRZ format equivalent and a coherent clock signal, comprising: input means responsive to said data for generating a first pulse for each transition of said data; generator means for generating a series of second pulses in accordance with a predetermined time sequence, said time sequence being determinable independently of the period of said data, said first pulses being applied to said generator means for restarting said time sequence; means responsive to said first and second pulses for generating said coherent clock signal, said clock signal comprising a wave which changes state upon the occurence of a first or a second pulse; and logic means responsive to said first and second pulses and said clock signal for generating said NRZ format equivalent of said digital data in synchronism with said clock signal.
Claim 3
Dependent Claim
66 words
Apparatus according to claim 1 wherein said generator means comprises: clock generator means for generating a train of clock pulses at a frequency which is substantially higher than the frequency of said digital data; and a ring counter, said ring counter receiving and counting said clock pulses, said first pulses being applied to said ring counter for resetting said ring counter to a predetermined starting count.
Claim 4
Dependent Claim
35 words
Apparatus according to claim 2 wherein said generator means further comprises: logic means for sensing a predetermined count in said ring counter and for generating said second pulses upon the occurrence of said predetermined count.
Claim 5
Dependent Claim
40 words
Apparatus according to claim 3 wherein each of said second pulses from said ring counter is indicative of the absence of a transition of said digital data for at least one half of a bit cell of said digital data.
Claim 6
Dependent Claim
72 words
Apparatus according to claim 4 wherein said serial digital data is phase encoded in accordance with a double density format, and wherein said generator means further comprises: logic means for generating a third pulse when at least one and a half bit cells of said data have occurred without a transition thereof, said third pulse being applied to said coherent clock signal generating means for establishing the phase of said square wave.
Claim 7
Dependent Claim
47 words
Apparatus according to claim 4 wherein the frequency of said train of clock pulses is a predetermined multiple of the frequency of said digital data whereby changes in the frequency of said data may be compensated for by changing the frequency of said train of clock pulses.
Claim 8
Dependent Claim
49 words
Apparatus according to claim 1 wherein said serial digital data is phase encoded in accordance with any bi-phase or double density format and wherein said logic means is operative to generate a plurality of NRZ encoded output signals, one for each of said bi-phase and double density input formats.
Claim 9
Dependent Claim
31 words
Apparatus according to claim 1 wherein said means for generating said coherent clock signal comprises: bi-stable circuit means which changes state upon the occurrence of a first or a second pulse.
Claim 10
Dependent Claim
55 words
Apparatus according to claim 1 wherein said serial digital data is phase encoded in accordance with a double density format and wherein the time interval between the first-occurring second pulse of said series of second pulses and the preceding first pulse is approximately equal to one half of a bit cell of said digital data.
Claim 11
Dependent Claim
34 words
Apparatus according to claim 9 wherein the time interval between consecutive second pulses of said sEries of second pulses is at least equal to one half of a bit cell of said digital data.
Claim 12
Dependent Claim
95 words
Apparatus according to claim 10 wherein said logic means comprises: bi-stable circuit means having a set input terminal and a reset input terminal; first means for comparing said first pulses and said clock signal and for applying a signal to said reset input terminal when a predetermined coincidence condition exists; and second means for comparing said second pulses and said clock signal and for applying a signal to said set input terminal when a predetermined coincidence condition exists, the output of said bi-stable circuit means comprising the NRZ format equivalent of said double density data.
Claim 13
Dependent Claim
64 words
Apparatus according to claim 11 wherein said first and second comparing means operate to examine the state of said digital data at the end of each bit cell and to reset said circuit means when a first pulse occurs at the end of a bit cell and to set said circuit means when a second pulse occurs at the end of a bit cell.
Claim 14
Dependent Claim
77 words
Apparatus according to claim 10 wherein said generator means further comprises: logic means responsive to the occurrence of a second pulse in said series of second pulses for inhibiting the generation of additional second pulses and for generating a sync pulse when at least an additional half bit cell of said data has occurred without a transition thereof, said sync pulse being applied to said clock signal generating means for establishing the phase of said square wave.
Claim 15
Dependent Claim
63 words
Apparatus according to claim 1 wherein said serial digital data is phase encoded in accordance with a bi-phase format and wherein the time interval between the first-occurring second pulse of said series of second pulses and the preceding first pulse is more than one half of a bit cell of said digital data and less than one bit cell of said digital data.
Claim 16
Dependent Claim
44 words
Apparatus according to claim 14 wherein said serial digital data is phase encoded in accordance with a bi-phase level format and wherein said logic means comprises: means for comparing said second pulses and said digital data, said comparing means providing said NRZ format equivalent.
Claim 17
Dependent Claim
51 words
Apparatus according to claim 15 wherein said comparing means comprises: bi-stable circuit means having true and false states, said circuit means going true if said digital data is high when a second pulse occurs, and said circuit means going false if said digital data is low when a second pulse occurs.
Claim 18
Dependent Claim
70 words
Apparatus according to claim 14 said serial digital data is phase encoded in accordance with a bi-phase level format and wherein said logic means comprises: a bi-stable flip-flop having a set input terminal, a reset input terminal and a clock input terminal, said set and reset input terminals receiving said digital data and the inverse of said digital data, respectively, said second pulses being applied to said clock input terminal.
Claim 19
Dependent Claim
65 words
Apparatus according to claim 1 wherein said serial digital data is phase encoded in accordance with a bi-phase format and wherein said means for generating said coherent clock signal comprises: first bi-stable circuit means having a set input terminal and a reset input terminal, said first pulses being applied to said set input terminal and said second pulses being applied to said reset input terminal.
Claim 20
Dependent Claim
67 words
Apparatus according to claim 18 wherein said logic means comprises: second bi-stable circuit means having a set input terminal and a reset input terminal, said second pulses being applied to said reset input terminal; and means for comparing said first pulses and said clock signal and for applying a signal to said set input terminal of said second bi-stable circuit means when a predetermined coincidence condition exists.
Claim 21
Dependent Claim
59 words
Apparatus according to claim 19 wherein said comparing means is operative to sense the existence of a first pulse at the middle of each bit cell of said data whereby said second bi-stable circuit means is set wheN a first pulse occurs at the middle of a bit cell and is reset upon the occurrence of every second pulse.
Claim 22
Dependent Claim
76 words
Apparatus according to claim 20 wherein said second bi-stable circuit means has normal and complementary output terminals, wherein said normal output terminal of said second bi-stable circuit means provides the NRZ format equivalent where said data is phase encoded in accordance with a bi-phase mark format and wherein said complementary output terminal of said second bi-stable circuit means provides the NRZ format equivalent where said data is phase encoded in accordance with a bi-phase space format.
Claim 23
Dependent Claim
183 words
Apparatus for converting serial digital data, phase encoded in accordance with a self-clocking format, to its NRZ format equivalent and a coherent clock signal, comprising: means operative independently of said data for generating a series of pulses in accordance with a predetermined time sequence, the period of said pulses being determinable independently of the period of said data, said data being applied to said generating means only for re-starting said time sequence upon the occurrence of a transition of said data; means responsive to said data and said pulses for generating said coherent clock signal, said clock signal providing a clock indication upon the occurrence of a transition of said data or upon the occurrence of one of said pulses; and means responsive to said data and said pulses for generating said NRZ format equivalent of said data. 23 Apparatus according to claim 22 further comprising: input means responsive to said data for generating a pulse upon the occurrence of a transition of said data, said pulse being applied to said means for generating a series of pulses for re-starting said time sequence.
Claim 24
Dependent Claim
111 words
Apparatus according to claim 22 wherein said means for generating a series of pulses comprises: clock generator means for generating a train of clock pulses at a frequency which is substantially higher than the frequency of said digital data; and a ring counter, said ring counter receiving and countering said clock pulses, said ring counter being reset to a predetermined starting count upon the occurrence of a transition of said data. 25 Apparatus according to claim 24 wherein said means for generating a series of pulses further comprises: logic means for sensing a predetermined count in said ring counter and for generating a pulse upon the occurrence of said predetermined count.
Claim 25
Dependent Claim
39 words
Apparatus according to claim 25 wherein each of said pulses of said series of pulses is indicative of the absence of a transition of said digital data for at least one-half of a bit cell of said digital data.
Claim 26
Dependent Claim
220 words
Apparatus according to claim 22 wherein said serial digital data is phase encoded in accordance with any bi-phase or double density format and wherein said means for generating said NRZ format equivalent is operative to generate a plurality of NRZ encoded output signals, one for each of said bi-phase and double density input formats. 28 Apparatus for converting serial digital data, phase encoded in accordance with a self-clocking format, to its NRZ format equivalent and a coherent clock signal comprising: input means responsive to said data for generating a first pulse for each transition of said data; generator means responsive to said first pulses for generating at least one second pulse a predetermined time interval after the occurence of each of said first pulses, said time interval being determinable independently of the period of said data, each of said first pulses re-starting said predetermined time interval, whereby each of said second pulses is indicative of the absence of a transition of said data for at least said predetermined time interval; means responsive to said first and second pulses for generating said coherent clock signal, said clock signal providing a clock indication upon the occurrence of a first or a second pulse, and logic means responsive to said first and second pulses for generating said NRZ format equivalent of said data.
Claim 27
Dependent Claim
25 words
Apparatus according to claim 28 wherein said clock signal comprises a wave which changes state upon the occurrence of a first or a second pulse.
Claim 28
Dependent Claim
41 words
Apparatus according to claim 28 wherein said logic means is further responsive to said clock signal for generating said NRZ format equivalent of said digital data in synchronism with said clock signal and independently of the transitions of said digital data.
Claim 29
Dependent Claim
37 words
Apparatus according to claim 1 wherein said generator means operates to generate said second pulses independently of the occurrence of said first pulses from said input means, said first pulses operating only to re-start said time sequence.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-12-05 | 1976-06-05 | 1976-12-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-12-05 | 1980-06-05 | 1980-12-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-12-05 | 1984-06-05 | 1984-12-05 | $7700.00 | Window Closed / Lapsed |