Liquid crystal drive circuit for driving a liquid crystal display element having scanning and signal electrodes arranged in matrix form

Claim 2

A liquid crystal drive circuit for driving a liquid crystal display element having scanning and signal electrodes arranged in matrix form, comprising: signal electrode voltage output means comprising a variable voltage divider including voltage-dividing series-connected resistors and a variable resistor, for dividing a reference liquid crystal drive voltage and outputting a 1/n bias signal electrode voltage, where n is a number greater than one; scanning electrode voltage output means comprising a series circuit including voltage-dividing resistors, for dividing the reference liquid crystal drive voltage and outputting at least a nonselection high level voltage (V1) and a nonselection low level voltage as scanning electrode voltages; first liquid crystal display element drive signal output means comprising first buffer circuit means for receiving a selection high level voltage (V0) from said signal electrode voltage output means and outputting a signal electrode voltage (V0') of the same level as that of said selection high level voltage (V0) from said signal electrode voltage output means, and a first operational amplifier for receiving a nonselection high level voltage (V1) as the scanning electrode voltage from said scanning electrode voltage output means and the selection high level voltage (V0') as the signal electrode voltage from said first buffer circuit means, and for outputting a nonselection high level signal electrode voltage (V2') having an inverted voltage level of the selection high level voltage (V0') output from said first buffer circuit means as the signal electrode voltage using the nonselection high level voltage (V1) from said scanning electrode voltage output means as a reference; and second liquid crystal display element drive signal output means comprising second buffer circuit means for receiving a selection low level voltage (V5) as the signal electrode voltage from said signal electrode voltage output means and for outputting a selection low level voltage (V5') as the signal electrode voltage having the same level as that of siad selection low level voltage (V5) from said signal electrode voltage output means, and a second operational amplifier for receiving a nonselection low level voltage (V4) as the scanning electrode voltage from said scanning electrode voltage output means and the selection low level voltage (V5') as the signal electrode voltage from said second buffer circuit means, and for outputting a nonselection low level voltage (V3') as the signal electrode voltage having an inverted voltage level of the selection low level voltage (V5') from said second buffer circuit means as the signal electrode voltage using the nonselection low level voltage (V4) from said scanning electrode voltage output means as a reference.

Claim 3

A liquid crystal drive circuit for driving a liquid crystal display element having scanning and signal electrodes arranged in matrix form, comprising: signal electrode voltage output means, comprising a variable voltage divider including voltage-dividing series-connected resistors and a variable resistor, for dividing a reference liquid crystal drive voltage and outputting a 1/n bias signal electrode voltage, where n is a number greater than one; scanning electrode voltage output means, comprising a series circuit including voltage-dividing resistors, for dividing the reference liquid crystal drive voltage and outputting at least a nonselection high level voltage (V1) and a nonselection low level voltage (V4) as scanning electrode voltages; first liquid crystal display element drive signal output means comprising first buffer circuit means for receiving a nonselection high level voltage (V2) as a signal electrode voltage from said signal electrode voltage output means and outputting a nonselection high level voltage (V2') as a signal electrode voltage of the same level as that of the nonselection high level voltage (V2) from said signal electrode voltage output means, and a first operational amplifier for receiving a nonselection high level voltage (V1) as the scanning electrode voltage from said scanning electrode voltage output means and the nonselection high level voltage (V2') as the signal electrode voltage from said first buffer circuit means, and for outputting a selection high level voltage (V0') having an inverted voltage level of the nonselection high level voltage (V2') output from said first buffer circuit means as the signal electrode voltage using the nonselection high level voltage (V1) from said scanning electrode voltage as a reference; and second liquid crystal display element drive signal output means comprising second buffer circuit means for receiving a nonselection low level voltage (V3) as the signal electrode voltage from said signal electrode voltage output means and for outputting a nonselection low level voltage (V3') as the signal electrode voltage having the same level as that of said nonselection low level voltage (V3) from said signal electrode voltage output means, and a second operational amplifier for receiving a nonselection low level voltage (V4) as the scanning electrode voltage from said scanning electrode voltage output means and the nonselection low level voltage (V3') as the signal electrode voltage from said second buffer circuit means, and for outputting a selection low level voltage (V5') as the signal electrode voltage having an inverted voltage level of the nonselection low level voltage (V3') from said second buffer circuit means as the signal electrode voltage using the nonselection low level voltage (V4) from said scanning electrode voltage output means as a reference.

Claim 4

A liquid crystal drive circuit for driving a liquid crystal display element having scanning and signal electrodes arranged in matrix form, comprising: signal electrode voltage output means, comprising a variable voltage divider including voltage-dividing series-connected resistors and a variable resistor, for dividing a reference liquid crystal drive voltage and outputting a 1/n bias signal electrode voltage, where n is a number greater than one; scanning electrode voltage output means, comprising a series circuit including voltage-dividing resistors, for dividing the reference liquid crystal drive voltage and outputting at least a nonselection high level voltage (V1) and a nonselection low level voltage (V4) as scanning electrode voltages; first liquid crystal display element drive signal output means comprising first buffer circuit means for receiving a nonselection high level voltage (V2) as a signal electrode voltage from said signal electrode voltage output means and outputting a nonselection high level voltage (V2') as a signal electrode voltage of the same level as that of the nonselection high level voltage (V2) from said signal electrode voltage output means, and a first operational amplifier for receiving a nonselection high level voltage (V1) as the scanning electrode voltage from said scanning electrode voltage output means and the nonselection high level voltage (V2') as the signal electrode voltage from said first buffer circuit means, and for outputting a selection high level voltage (V0') having an inverted voltage level of the nonselection high level voltage (V2') output from said first buffer circuit means as the signal electrode voltage using the nonselection high level voltage (V1) from said scanning electrode voltage as a reference; and second liquid crystal display element drive signal output means comprising second buffer circuit means for receiving a nonselection low level voltage (V3) as the signal electrode voltage from said signal electrode voltage output means and for outputting a nonselection low level voltage (V3') as the signal electrode voltage having the same level as that of said nonselection low level voltage (V3) from said signal electrode voltage output means, and a second operational amplifier for receiving a nonselection low level voltage (V4) as the scanning electrode voltage from said scanning electrode voltage output means and the nonselection low level voltage (V3') as the signal electrode voltage from said second buffer circuit means, and for outputting a selection low level voltage (V5') as the signal electrode voltage having an inverted voltage level of the nonselection low level voltage (V3') from said second buffer circuit means as the signal electrode voltage using the nonselection low level voltage (V4) from said scanning electrode voltage output means as a reference.