Semiconductor device having floating and control gates

Claim 2

A semiconductor device comprising: source and drain regions between which a channel region is formed, a gate insulating layer provided on said channel region, a floating gate provided on said gate insulating layer, a composite insulating layer provided on said floating gate and including a plurality of insulating layers which are different from one another in their properties, and a control gate provided on said composite insulating layer, wherein said floating gate, said control gate, and said composite insulating layer are self-aligned by etching using a single mask, wherein the widths of said floating and said control gates are substantially the same in the length direction of said channel region, and wherein the end portions of said composite insulating layer extend in the length direction of said channel region beyond the end portions of said floating and control gates.

Claim 3

A semiconductor device according to claim 1, wherein said composite insulating layer includes a silicon nitride layer.

Claim 4

A semiconductor device according to claim 1, wherein said composite insulating layer includes an SiO 2 layer formed by a chemical vapor deposition method.

Claim 5

A semiconductor device according to claim 1, wherein said composite insulating layer comprises a silicon nitride layer and an SiO 2 layer formed on said silicon nitride layer by thermal oxidation of the surface of said silicon nitride layer.

Claim 6

A semiconductor device according to claim 1, wherein said floating gate is made of polysilicon layer; and said composite insulating layer comprises a first SiO 2 (silicon dioxide) layer formed by thermal oxidation of said floating gate, a silicon nitride layer formed on said first SiO 2 layer, and a second SiO 2 layer formed on said silicon nitride layer by a chemical vapor deposition method.

Claim 7

A semiconductor device according to claim 1, wherein the end portions of said composite insulating layer also extend in the channel-width direction of said channel region beyond the end portions of said floating gate.

Claim 8

A semiconductor device comprising: source and drain regions between which a channel region is formed, a gate insulating layer provided on said channel region, a floating gate provided on said gate insulating layer, a composite insulating layer provided on said floating gate and including a plurality of insulating layers which are different from one another in their properties, and a control gate provided on said composite insulating layer, wherein said floating gate, said control gate, and said composite insulating layer are self-aligned by anisotropic etching using a single resist pattern, wherein the widths of said floating and said control gates are substantially the same in the length direction of said channel region, and wherein the end portions of said composite insulating layer extend in the length direction of said channel region beyond the end portions of said floating and control gates.

Claim 9

A semiconductor device comprising: source and drain regions between which a channel region is formed, a gate insulating layer provided on said channel region, a floating gate provided on said gate insulating layer, a composite insulating layer provided on said floating gate and including a plurality of insulating layers which are different from one another in their properties, and a control gate provided on said composite insulating layer, wherein said floating gate, said control gate, and said composite insulating layer are self-aligned by anisotropic etching using a single resist pattern, wherein the widths of said floating and said control gates are substantially the same in the length direction of said channel region, and wherein the end portions of said composite insulating layer extend in the length direction of said channel region beyond the end portions of said floating and control gates.