C-MOS technology base cell

Claim 1

A CMOS integrated circuit, comprising: a plurality of base cells each base cell having a first transistor of first channel type, having source and drain regions of first conductivity type located in a second conductivity type portion of a semiconductor substrate, and a gate electrode located between the source and drain regions of first conductivity type; a second transistor of second channel type, having source and drain regions of second conductivity type located in a tub of first conductivity type in said semiconductor substrate, and a gate electrode located between the source and drain regions of second conductivity type, a direction from the source region to the drain region of the first transistor being parallel to a direction from the source region to the drain region of the second transistor; a plurality of said base cells each having a plurality of first polysilicon interconnects positioned parallel to the direction from the source region to the drain region of each transistor, and each having a plurality of second metal interconnects positioned perpendicular to and crossing said first interconnects but insulated therefrom except at selected contact locations where a contact is desired at a cross point; said base cells being arranged adjacent each other in a direction perpendicular to said direction from the source region to the drain region of said base cells, said direction from the source region to the drain region of each cell being parallel to said direction from the source region to the drain region of the adjacent cells; at least one of said second metal interconnects in at least one of said base cells running perpendicular to the direction from the source region to the drain region of the transistors of that base cell, being positioned between the first and second transistors of that base cell, and extending from a position between the transistors of the adjacent cell on one side of that base cell to a position between the transistors of the adjacent cell on the other side of that base cell; at least one other of said second metal interconnects being a power supply line and extending over one of the source or drain regions of the first transistor of each base cell; and at least one further second interconnect being a second power supply line and extending over one of the source or drain regions of the second transistor of each base cell.