Writing speed in multi-port static rams

Claim 2

In a matrix-array read-write memory device of the type having a plurality of individually addressable discrete memory cells, having a plurality of discrete ports for accessing individual memory cells for writing or reading data in said memory cells, a memory cell accessible from a first and a second port, and including a bi-stable core cell having a first state representing a logic 1 bit and a second state representing a logic 0 bit and having a complementary pair of input-output terminals CC1 and CC2, a first-port word-select line and a second-port word-select line each coupled to said terminals CC1 and CC2, a first port column select input and a second port column select input each coupled to said terminals CC1 and CC2, a first-port bit-line BL1 and a second-port bit-line BR1 each coupled to said terminal CC1, a first-port bit-line BL2 and a second-port bit-line BR2 each coupled to said terminal CC2, and write circuit means coupled to the bit-lines of one of said ports and selectively operable to write data into said core cell by applying a logic 1 signal to one of said bit-lines and a logic 0 signal to the other of said bit-lines, said device further comprising: gated write-bias means operating in cooperation with said write circuit means and coupled to one of said bit-lines to apply a write bias thereto, including a plurality of write-bias gates, one of said write-bias gates being provided for and associated with each of said plurality of ports, and wherein each of said write-bias gates is coupled between the bit-lines of its associated port and a source of logic-signal voltage, and further including means to cause each said gate to pass said logic-signal voltage to the bit-lines of its associated port in response to a write operation on another port, and to not pass said logic-signal voltage to the bit-lines of its associated port in the absence of a write operation on another port.

Claim 3

The device of claim 1 wherein said write-bias means comprises: a source of logic-signal voltage, and a switch means, operable between a closed state and an open state and coupled between said source of logic-signal voltage and one of said bit-lines, to supply thereto said logic-signal voltage from said source when said switch means is closed.

Claim 4

The device of claim 2 wherein said switch means comprises an FET having source, drain and gate electrodes, and wherein one of said source and drain electrodes is connected to said source of logic-signal voltage and the other of said source and drain electrodes is connected to one of said bit-lines.

Claim 5

The device of claim 3 further including means to couple a logic 1 signal to said gate electrode for a preselected interval during the duration of said write signal.

Claim 6

The device of claim 2 wherein said source of logic-signal voltage supplies a logic 1 voltage level.

Claim 7

The device of claim 1 further comprising four pass-gates, and wherein each of said bit-lines coupled to one of the terminals of said core cell is so coupled by one of said four pass-gates.

Claim 8

The device of claim 6 wherein each of said pass-gates comprises an FET having source, gate and drain electrodes, and wherein one of said source and drain electrodes of each said pass-gate is connected to one of said bit-lines, and the other of said source and drain electrodes is connected to one of said core cell terminals.

Claim 9

The device of claim 7 wherein the gate electrode of one of said FETs connected to terminal CC1 is connected to said first-port word line, the gate electrode of the other of said FETs connected to terminal CC1 is connected to said second-port word line, the gate electrode of one of said FETs connected to terminal CC2 is connected to said first-port word line, and the gate electrode of the other of said FETs connected to terminal CC2 is connected to said second-port word line.

Claim 10

The device of claim 1 wherein said plurality of ports are two in number and said plurality of write-bias gates are two in number.

Claim 11

In a memory device having a plurality of memory cells, a first port and a second port, at least one of said cells being provided with a first pair of bit lines accessible to said first port and a second pair of bit-lines accessible to said second port, for reading binary data from said cell and writing data into said cell from said ports, a first write circuit means coupled to said first port for writing data into said one cell, the improvement comprising: a first gated write-bias means operating in cooperation with said first write circuit means and coupled to one of said second pair of bit-lines to apply thereto a write bias in response to a write through the first port, a second write circuit means coupled to said second port for writing data into said one cell, and a second gated write-bias means operating in cooperation with said second write circuit means and coupled to one of said first pair of bit lines to apply thereto a write-bias in response to a write through the second port.

Claim 12

In a memory device having a plurality of memory cells, a first port and a second port, at least one of said cells being provided with a first pair of bit lines accessible to said first port and a second pair of bit-lines accessible to said second port, for reading binary data from said cell and writing data into said cell from said ports, a first write circuit means coupled to said first port for writing data into said one cell, the improvement comprising: a first gated write-bias means operating in cooperation with said first write circuit means and coupled to one of said second pair of bit-lines to apply thereto a write bias in response to a write through the first port, a second write circuit means coupled to said second port for writing data into said one cell, and a second gated write-bias means operating in cooperation with said second write circuit means and coupled to one of said first pair of bit lines to apply thereto a write-bias in response to a write through the second port.

Claim 13

The memory device of claim 10 wherein said first gated write-bias means is coupled to each bit-line of said second pair of bit-lines.

Claim 14

The memory device of claim 11 wherein said first gated write-bias means comprises a first write-bias gate coupled between one of said first pair of bit-lines and a source of logic-signal voltage, and a second write-bias gate coupled between the other of said first pair of bit-lines and said source of logic-signal voltage.

Claim 15

The memory device of claim 12 further including means to cause said first write-bias gate to pass said logic-signal voltage to its coupled bit-line in response to a write operation on said first port, and to not pass said logic-signal voltage to its coupled bit-line in the absence of a write operation on said first port.

Claim 16

The memory device of claim 10 wherein said first gated write-bias means is coupled to each bit-line of said second pair and said second write-bias means is coupled to each bit-line of said first pair.

Claim 17

The memory device of claim 10 wherein said first gated write-bias means comprises a first write-bias gate coupled between a source of logic-signal voltage and one bit-line of said second pair, and further including means to cause said first write-bias gate to pass said logic-signal voltage to its coupled bit-line in response to a write operation on said first port, and to not pass said logic-signal voltage to its coupled bit-line in the absence of a write operation on said first port.

Claim 18

The memory device of claim 10 wherein said second gated write-bias means comprises a first write-bias gate coupled between a source of logic-signal voltage and one bit-line of said first pair, and further including means to cause said first write-bias gate to pass said logic-signal voltage to its coupled bit-line in response to a write operation on said second port, and to not pass said logic-signal voltage to its coupled bit-line in the absence of a write operation on said second port.

Claim 19

The memory device of claim 10 further including a second write circuit means coupled to said second port for writing data into said cell, the improvement further comprising: said first gated write-bias means being coupled to each of said second pair of bit-lines to apply thereto a write bias; a second gated write-bias means operating in cooperation with said second write circuit means and coupled to each of said first pair of bit-lines to apply thereto a write bias.

Claim 20

A memory device comprising: an array of core cells storing data, each core cell having a terminal from which a state may be sensed that indicates the data stored in the core cell and through which the state of the core cell may be changed by applying a write bias to the terminal, the array including a plurality of predetermined subsets; a first port, including a plurality of first bit lines, each first bit line corresponding to no more than one core cell in any predetermined subset, means for supplying first port cell select signals and first port subset select signals indicating respectively a selected first bit line in the plurality of first bit lines and a first selected subset in the plurality of predetermined subsets, means, responsive to first port cell select signals, for enabling the selected first bit line to be sensed or biased, means, responsive to first port subset select signals, for connecting each of the terminals of the first selected subset to first bit lines corresponding to the core cells in the first selected subset; a second port, including a plurality of second bit lines, each second bit line corresponding to no more than one core cell in any predetermined subset, means for supplying second port cell select signals and second port subset select signals indicating respectively a selected second bit line in the plurality of second bit lines and a second selected subset in the plurality of predetermined subsets, means, responsive to second port cell select signals, for enabling the selected second bit line to be sensed or biased, means, responsive to second port subset select signals, for connecting each of the terminals of the second selected subset to second bit lines corresponding to core cells in the second selected subset; first port read/write means, in cooperation with the first port, for sensing or biasing the plurality of first bit lines to effect reading or writing of data in selected core cells; second port read/write means, in cooperation with the second port, for sensing or biasing the plurality of second bit lines to effect reading or writing of data in selected core cells; first write bias means, in cooperation with the first port and connected to the plurality of second bit lines, for charging the second bit line corresponding to a given core cell during writing of data to the given core cell by the first read/write means; and second write bias mean, in cooperation with the second port and connected to the plurality of first bit lines, for charging the first bit line corresponding to a given cell during writing of data to the given cell by the second read/write means.

Claim 21

A memory device comprising: an array of core cells storing data, each core cell having a terminal from which a state may be sensed that indicates the data stored in the core cell and through which the state of the core cell may be changed by applying a write bias to the terminal, the array including a plurality of predetermined subsets; a first port, including a plurality of first bit lines, each first bit line corresponding to no more than one core cell in any predetermined subset, means for supplying first port cell select signals and first port subset select signals indicating respectively a selected first bit line in the plurality of first bit lines and a first selected subset in the plurality of predetermined subsets, means, responsive to first port cell select signals, for enabling the selected first bit line to be sensed or biased, means, responsive to first port subset select signals, for connecting each of the terminals of the first selected subset to first bit lines corresponding to the core cells in the first selected subset; a second port, including a plurality of second bit lines, each second bit line corresponding to no more than one core cell in any predetermined subset, means for supplying second port cell select signals and second port subset select signals indicating respectively a selected second bit line in the plurality of second bit lines and a second selected subset in the plurality of predetermined subsets, means, responsive to second port cell select signals, for enabling the selected second bit line to be sensed or biased, means, responsive to second port subset select signals, for connecting each of the terminals of the second selected subset to second bit lines corresponding to core cells in the second selected subset; first port read/write means, in cooperation with the first port, for sensing or biasing the plurality of first bit lines to effect reading or writing of data in selected core cells; second port read/write means, in cooperation with the second port, for sensing or biasing the plurality of second bit lines to effect reading or writing of data in selected core cells; first write bias means, in cooperation with the first port and connected to the plurality of second bit lines, for charging the second bit line corresponding to a given core cell during writing of data to the given core cell by the first read/write means; and second write bias mean, in cooperation with the second port and connected to the plurality of first bit lines, for charging the first bit line corresponding to a given cell during writing of data to the given cell by the second read/write means.

Claim 22

The memory device of claim 18, wherein each of the terminals of the core cells includes a complementary pair of nodes CC1, CC2; each of the first bit lines includes a first complementary pair of lines BR1, BR2; and each of the second bit lines includes a second complementary pair of lines BL1, BL2.