Data processor for changing the sequential format of inputted records

Claim 1

A data processing system for producing a series of output data words in response to a series of input data words, with the output data words having a different sequential format as compared with the sequential format of the data input words, said system comprising: a first memory for storing the input data words; a first address register connected to said first memory; a second memory for storing instruction words relating to the retrieval of the data words from said first memory; a second address register connected to said second memory; address generating circuitry connected to said second address register for generating successive address words and for sequentially introducing said successive address words to said second address register; first logic circuitry connected to said address generating circuitry for causing said successive address words to be sequentially introduced to said first address register during an input operational mode of said first memory; second logic circuitry connected to said first memory to pass the input data words sequentially to said first memory during said input operational mode; third logic circuitry for disabling said first logic circuitry and for causing instruction words to be sequentially introduced to said first address register from said second memory during an output operational mode to retrieve data words from said first memory in a sequence determined by said instruction words; and fourth logic circuitry connected to said first memory for causing data words retrieved from said first memory by said instruction words to pass out of the system as said output data words during said output operational mode.