Carry-bypass arithmetic logic unit

Claim 2

An arithmetic logic unit comprising: a plurality of sets of cells, each of said sets comprising a first, a second, a third and a fourth cell; and a carry bypass circuit coupled to said cells in each set, wherein each of said cells comprises: a propagate circuit responsive to a predetermined bit in a first operand T, a predetermined bit in a second operand B, a plurality of code bits (G0-G3) and a clock signal .0.1 for selectively providing a propagate bit P; a kill circuit responsive to said predetermined bits in said first and said second operands T and B, a clock signal .0.1* which comprises an inverted form of said clock signal .0.1, said propagate bit P and a carry-in bit C in on a carry-in bit line for selectively providing a carry-out bit C out on a carry-out bit line; and a sum circuit responsive to said propagate bit P, said carry-in bit C in and a code bit G4 for selectively providing a sum bit NS wherein NS=P⊕G4·C in ; and said carry bypass circuit comprises: a first bypass circuit responsive to said propagate bit P from said propagate circuit in each of said first, said second, said third and said fourth cells, said carry-in bit C in on said carry-in bit line of said first cell and a clock signal .0.2* for providing said carry-out bit C out on said carry-out bit line of said fourth cell; and a second bypass circuit responsive to said propagate bit P from said propagate circuits in said second and said third cells, said clock signal .0.2* and said carry-out bit C out on said carry-out bit line of said first cell for providing said carry-out bit C out on said carry-out bit line of said third cell.

Claim 3

An arithmetic logic unit according to claim 1 wherein said propagate circuit comprises a plurality of transistors which are responsive to predetermined combinations of said predetermined bits of said first and said second operands T and B and predetermined combinations of said plurality of code bits (G0-G3) for selectively providing said propagate bit P.

Claim 4

An arithmetic logic unit according to claim 2 wherein said plurality of transistors comprise a means for coupling predetermined ones of said transistors to a source of said code bits (G0-G3) and means responsive to said predetermined bits of said first and said second operands T and B for selectively providing said propagate bit P.

Claim 5

An arithmetic logic unit according to claim 1 wherein said kill circuit comprises a node A on said carry-out bit line; means responsive to said clock signal .0.1 for precharging said node A to a first predetermined potential and means responsive to said clock signal .0.1*, said predetermined bits of said first and said second operand T and B, said propagate bit P and said carry-in bit C in for selectively discharging said node A to a second predetermined potential.

Claim 6

An arithmetic logic unit according to claim 4 wherein said discharging means comprises: first means for discharging said node A when said predetermined bits of said first and second operand T and B are at said second predetermined potential; and second means for discharging said node A when said bit of one of said operands T and B is at said first predetermined potential, said bit of the other of said operands T and B is at said second predetermined potential, said propagate bit P is at said first predetermined potential and said carry-in bit C in is at said second predetermined potential.

Claim 7

An arithmetic logic unit according to claim 1 wherein said sum circuit comprises: a NAND circuit responsive to said carry-in bit C in and said code bit G4 for providing an output and an exclusive OR circuit responsive to said output of said NAND circuit and said propagate bit P for providing said sum bit NS, wherein NS=P⊕G4·C in .

Claim 8

An arithmetic logic unit comprising: a plurality of cells wherein each of said cells comprises: first circuit means responsive to a predetermined bit in a first operand T, a predetermined bit in a second operand B, a plurality of code bits (G0-G3) and a clock signal .0.1 for providing a propagate bit P; second circuit means responsive to said propagate bit P, a code bit G4 and a carry-in bit C in for providing a sum bit NS, wherein NS=P⊕G4·C in , G4=0 and NS=P when said arithmetic logic unit is performing a logical operation and G4=1 and NS=P⊕C in when said arithmetic logic unit is performing an arithmetic operation; and third circuit means responsive to said predetermined bit in said first operand T, said predetermined bit in said second operand B, said propagate bit P, a clock signal .0.1* which comprises an inverted form of said clock signal .0.1, and said carry-in bit C in for providing a carry-out bit C out .

Claim 9

An arithmetic logic unit comprising: a plurality of cells wherein each of said cells comprises: first circuit means responsive to a predetermined bit in a first operand T, a predetermined bit in a second operand B, a plurality of code bits (G0-G3) and a clock signal .0.1 for providing a propagate bit P; second circuit means responsive to said propagate bit P, a code bit G4 and a carry-in bit C in for providing a sum bit NS, wherein NS=P⊕G4·C in , G4=0 and NS=P when said arithmetic logic unit is performing a logical operation and G4=1 and NS=P⊕C in when said arithmetic logic unit is performing an arithmetic operation; and third circuit means responsive to said predetermined bit in said first operand T, said predetermined bit in said second operand B, said propagate bit P, a clock signal .0.1* which comprises an inverted form of said clock signal .0.1, and said carry-in bit C in for providing a carry-out bit C out .

Claim 10

An arithmetic logic unit according to claim 7 wherein said third circuit means comprises: a node A corresponding to said carry-out bit C out ; means for precharging said node A to a first predetermined potential; and means responsive to said predetermined bit in said first operand T, said predetermined bit in said second operand B, said propagate bit P, said clock signal .0.1* and said carry-in bit C in for discharging said node A to a second predetermined level when said predetermined bits in said first and said second operands T and B are at said second predetermined potential and when one of said predetermined bits is at said second predetermined potential, the other, one of said predetermined bits is at said first predetermined potential, said propagate bit P is at said first predetermined potential and said carry-in bit C in is at said second predetermined potential.

Claim 11

An arithmetic logic unit according to claim 7 wherein said plurality of cells are grouped in sets of four cells, each of said sets comprises a first, a second, a third and a fourth one of said plurality of cells and further comprising: a bypass circuit coupled to each of said sets wherein each of said bypass circuits comprises means responsive to said propagate bit P from predetermined ones of said first, said second, said third and said fourth cell in each of said sets, said carry-in bit applied to a predetermined one of said first, said second, said third and said fourth cell in each of said sets, and a clock signal .0.2* for providing said carry-out bit C out from a predetermined one of said first, said second, said third and said fourth cell in each of said sets.

Claim 12

An arithmetic logic circuit according to claim 9 wherein said bypass circuit comprises: a first bypass circuit responsive to said propagate bit P from each of said first, said second, said third and said fourth cells, said carry-in bit C in applied to said first cell and said clock signal .0.2* for providing said carry-out bit C out from said fourth cell; and a second bypass circuit responsive to said propagate bit P applied to said second and said third cells, said clock signal .0.2* and said carry-out bit C out from said first cell for providing said carry-out bit C out from said third cell.

Claim 13

An arithmetic logic unit according to claim 8 comprising means responsive to said propagate bit P from certain cells in a set of said cells, a carry-in bit C in applied to a first cell in said set and a clock signal .0.2* for providing said carry-out bit C out from a fourth cell in said set.

Claim 14

An arithmetic logic unit according to claim 11 wherein said set comprises a first, a second, a third, and a fourth cell coupled in series, and said carry-out bit providing means comprises means for selectively causing said carry-in bit to bypass four of said cells in a set when all of said propagate bits have a first predetermined potential and to bypass two of said cells in said set when the middle two of said propagate bits have said first predetermined potential.

Claim 15

An arithmetic logic unit comprising: a plurality of sets of cells wherein each of said sets comprises a first, a second, a third and a fourth one of said cells and each of said cells comprises: first circuit means responsive to a predetermined bit in a first operand T, a predetermined bit in a second operand B, a plurality of code bits (G0-G3) and a clock signal .0.1 for providing a propagate bit P; and second circuit means responsive to said propagate bit P, a code bit G4 and a carry-in bit C in for providing a sum bit NS, wherein NS=P⊕G4·C in , G4=0 and NS=P when said arithmetic logic unit is performing a logical operation and G4=1 and NS=P⊕C in when said arithmetic logic unit is performing an arithmetic operation; and a bypass circuit coupled to each of said sets wherein each of said bypass circuits comprises means responsive to said propagate bit P from predetermined one of said first, said second, said third and said fourth cell in each of said sets, said carry-in bit applied to a predetermined one of said first, said second, said third and said fourth cells in each of said sets, and a clock signal .0.2* for providing said carry-out bit C out from a predetermined one of said first, said second, said third and said fourth cell in each of said sets.

Claim 16

An arithmetic logic unit comprising: a plurality of sets of cells wherein each of said sets comprises a first, a second, a third and a fourth one of said cells and each of said cells comprises: first circuit means responsive to a predetermined bit in a first operand T, a predetermined bit in a second operand B, a plurality of code bits (G0-G3) and a clock signal .0.1 for providing a propagate bit P; and second circuit means responsive to said propagate bit P, a code bit G4 and a carry-in bit C in for providing a sum bit NS, wherein NS=P⊕G4·C in , G4=0 and NS=P when said arithmetic logic unit is performing a logical operation and G4=1 and NS=P⊕C in when said arithmetic logic unit is performing an arithmetic operation; and a bypass circuit coupled to each of said sets wherein each of said bypass circuits comprises means responsive to said propagate bit P from predetermined one of said first, said second, said third and said fourth cell in each of said sets, said carry-in bit applied to a predetermined one of said first, said second, said third and said fourth cells in each of said sets, and a clock signal .0.2* for providing said carry-out bit C out from a predetermined one of said first, said second, said third and said fourth cell in each of said sets.

Claim 17

An arithmetic logic circuit according to claim 13 wherein said bypass circuit comprises: a first bypass circuit responsive to said propagate bit P from each of said first, said second, said third and said fourth cells, said carry-in bit C in applied to said first cell and said clock signal .0.2* for providing said carry-out bit C out from said fourth cell; and a second bypass circuit responsive to said propagate bit P applied to said second and said third cells, said clock signal .0.2* and said carry-out bit C out from said first cell for providing said carry-out bit C out from said third cell.

Claim 18

An arithmetic logic unit according to claim 13 comprising: third circuit means responsive to said predetermined bit in said first operand T, said predetermined bit in said second operand B, said propagate bit P, a clock signal .0.1* which comprises an inverted form of said clock signal .0.1, and said carry-in bit C in for providing a carry-out bit C out ; a node A corresponding to said carry-out bit C out ; means for precharging said node A to a first predetermined potential; and means responsive to said predetermined bit in said first operand T, said predetermined bit in said second operand B, said propagate bit P, said clock signal .0.1* and said carry-in bit C in for discharging said node A to a second predetermined level when said predetermined bits in said first and said second operands T and B are at said second predetermined potential and when one of said predetermined bits is at said second predetermined potential, the other one of said predetermined bits is at said first predetermined potential, said propagate bit P is at said first predetermined potential and said carry-in bit C in is at said second predetermined potential.

Claim 19

An arithmetic logic unit comprising: a plurality of cells wherein each of said cells comprises: first circuit means responsive to a predetermined bit in a first operand T, a predetermined bit in a second operand B, a plurality of code bits (G0-G3) and a clock signal .0.1 for providing a propagate bit P; second circuit means reponsive to said propagate bit P, a code bit G4 and a carry-in bit C in for providing a sum bit NS, wherein NS=P⊕G4·C in , G4=0 and NS=P when said arithmetic logic unit is performing a logical operation and G4=1 and NS=P⊕C in when said arithmetic logic unit is performing an arithmetic operation; and third circuit means responsive to said predetermined bit in said first operand T, said predetermined bit in said second operand B, said propagate bit P, a clock signal .0.1* which comprises an inverted form of said clock signal .0.1, and said carry-in bit C in for providing a carry-out bit C out ; a node A corresponding to said carry-out bit C out ; means for precharging said node A to a first predetermined potential; and means responsive to said predetermined bit in said first operand T, said predetermined bit in said second operand B, said propagate bit P, said clock signal .0.1* and said carry-in bit C in for discharging said node A to a second predetermined level when said predetermined bits in said first and said second operands T and B are at said second predetermined potential and when one of said predetermined bits is at said second predetermined potential, the other one of said predetermined bits is at said first predetermined potential, said propagate bit P is at said first predetermined potential and said carry-in bit C in is at said second predetermined potential.

Claim 20

An arithmetic logic unit comprising: a plurality of cells wherein each of said cells comprises: first circuit means responsive to a predetermined bit in a first operand T, a predetermined bit in a second operand B, a plurality of code bits (G0-G3) and a clock signal .0.1 for providing a propagate bit P; second circuit means reponsive to said propagate bit P, a code bit G4 and a carry-in bit C in for providing a sum bit NS, wherein NS=P⊕G4·C in , G4=0 and NS=P when said arithmetic logic unit is performing a logical operation and G4=1 and NS=P⊕C in when said arithmetic logic unit is performing an arithmetic operation; and third circuit means responsive to said predetermined bit in said first operand T, said predetermined bit in said second operand B, said propagate bit P, a clock signal .0.1* which comprises an inverted form of said clock signal .0.1, and said carry-in bit C in for providing a carry-out bit C out ; a node A corresponding to said carry-out bit C out ; means for precharging said node A to a first predetermined potential; and means responsive to said predetermined bit in said first operand T, said predetermined bit in said second operand B, said propagate bit P, said clock signal .0.1* and said carry-in bit C in for discharging said node A to a second predetermined level when said predetermined bits in said first and said second operands T and B are at said second predetermined potential and when one of said predetermined bits is at said second predetermined potential, the other one of said predetermined bits is at said first predetermined potential, said propagate bit P is at said first predetermined potential and said carry-in bit C in is at said second predetermined potential.