Patent US4764798A successfully refreshed from Google Patents.
US4764798A
Expired / Lapsed
US
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Master slice IC having n and p channel transistors
Assignee: Mitsubishi Electric Corp
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Filing: 1986-01-09
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Granted: 1988-08-16
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Expires: 2006-01-09
Abstract
Abstract A semiconductor integrated circuit device of the master slice type which is suitable for use both in digital and analog circuits. The device includes a plurality of parallel basic elements, each including a plurality of p channel MOS transistors having gate electrodes connected commonly and source and drain regions separated from each other and a plurality of n channel MOS transistors having gate electrodes connected commonly and source and drain regions separated from each other. The source and drain regions of the p and n channel MOS transistors arranged in corresponding positions of the basic elements are common.
Inventors
- 👤 Keiji Kawabata
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 22:11
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/90; H10D84/903; H10D84/907
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
280 words
A semiconductor integrated circuit device comprising: a plurality of first gate electrodes formed in a main surface of a semiconductor substrate and arranged parallel to one another, a plurality of first p type regions formed in said main surface of said semiconductor substrate below and orthogonal to said first gate electrodes, said first p type regions and said first gate electrodes forming a plurality of first p channel MOS transistors, a plurality of second p type regions formed in said main surface of said semiconductor substrate below and orthogonal to said first gate electrodes, said second p type regions being parallel to and separated from said first p type regions and forming, together with said first gate electrodes, a plurality of second p channel MOS transistors, said first gate electrodes covering and bridging said first and second p type regions, a plurality of second gate electrodes formed in said main surface of said semiconductor substrate and arranged parallel to one another and to said first gate electrodes, a plurality of first n type regions formed in said main surface of said semiconductor substrate below and orthogonal to said second gate electrodes, said first n type regions and said second gate electrodes forming a plurality of a first n channel MOS transistors, and a plurality of second n type regions formed parallel to and separate from said first n type regions in said main surface of said semiconductor substrate below and orthogonal to said second gate electrodes, said second n type regions forming, together with said second gate electrodes, a plurality of second n channel MOS transistors, said second gate electrodes covering and bridging said first and second n type regions.
Claim 2
Dependent Claim
280 words
A semiconductor integrated circuit device comprising: a plurality of first gate electrodes formed in a main surface of a semiconductor substrate and arranged parallel to one another, a plurality of first p type regions formed in said main surface of said semiconductor substrate below and orthogonal to said first gate electrodes, said first p type regions and said first gate electrodes forming a plurality of first p channel MOS transistors, a plurality of second p type regions formed in said main surface of said semiconductor substrate below and orthogonal to said first gate electrodes, said second p type regions being parallel to and separated from said first p type regions and forming, together with said first gate electrodes, a plurality of second p channel MOS transistors, said first gate electrodes covering and bridging said first and second p type regions, a plurality of second gate electrodes formed in said main surface of said semiconductor substrate and arranged parallel to one another and to said first gate electrodes, a plurality of first n type regions formed in said main surface of said semiconductor substrate below and orthogonal to said second gate electrodes, said first n type regions and said second gate electrodes forming a plurality of a first n channel MOS transistors, and a plurality of second n type regions formed parallel to and separate from said first n type regions in said main surface of said semiconductor substrate below and orthogonal to said second gate electrodes, said second n type regions forming, together with said second gate electrodes, a plurality of second n channel MOS transistors, said second gate electrodes covering and bridging said first and second n type regions.
Claim 3
Dependent Claim
42 words
The semiconductor integrated circuit device as claimed in claim 1, wherein said first and second p type regions form first and second common p regions, respectively, and said first and second n type regions form first and second common n regions, respectively.
Claim 4
Dependent Claim
345 words
A semiconductor integrated circuit device comprising: a plurality of first p type regions formed in a main surface of a semiconductor substrate and arranged parallel to one another, a plurality of second p type regions formed in said main surface of said semiconductor substrate separately from and parallel to said first p type regions and arranged parallel to one another, a plurality of first common gate electrodes formed on said main surface of said semiconductor substrate and arranged parallel to one another, each of said first common gate electrodes being arranged between adjacent ones of said first p type regions and between adjacent ones of said second p type regions, a plurality of first n type regions formed in said main surface of said semiconductor substrate separately from said first and second p type regions and parallel to one another, a plurality of second n type regions formed in said main surface of said semiconductor substrate separately from and parallel to said first and second p type regions and said first n type regions and parallel to one another, a plurality of second parallel common gate electrodes formed on said main surface of said semiconductor substrate separately from said first parallel common gate electrodes, each of said second parallel common gate electrodes being arranged between adjacent ones of said first n type regions and between adjacent ones of said second n type regions, whereby adjacent ones of said first p type regions and one of said first common gate electrodes disposed between said adjacent first p type regions constitute a first p channel MOS transistor, adjacent ones of said second p type regions and said one of said first common gate electrodes constitute a second p channel MOS transistor, adjacent ones of said first n type regions and one of said second common gate electrodes disposed between said adjacent first n type regions constitute a first n channel MOS transistor, and adjacent ones of said second n type regions and said one of said second common gate electrodes constitute a second n channel MOS transistor.
Claim 5
Dependent Claim
345 words
A semiconductor integrated circuit device comprising: a plurality of first p type regions formed in a main surface of a semiconductor substrate and arranged parallel to one another, a plurality of second p type regions formed in said main surface of said semiconductor substrate separately from and parallel to said first p type regions and arranged parallel to one another, a plurality of first common gate electrodes formed on said main surface of said semiconductor substrate and arranged parallel to one another, each of said first common gate electrodes being arranged between adjacent ones of said first p type regions and between adjacent ones of said second p type regions, a plurality of first n type regions formed in said main surface of said semiconductor substrate separately from said first and second p type regions and parallel to one another, a plurality of second n type regions formed in said main surface of said semiconductor substrate separately from and parallel to said first and second p type regions and said first n type regions and parallel to one another, a plurality of second parallel common gate electrodes formed on said main surface of said semiconductor substrate separately from said first parallel common gate electrodes, each of said second parallel common gate electrodes being arranged between adjacent ones of said first n type regions and between adjacent ones of said second n type regions, whereby adjacent ones of said first p type regions and one of said first common gate electrodes disposed between said adjacent first p type regions constitute a first p channel MOS transistor, adjacent ones of said second p type regions and said one of said first common gate electrodes constitute a second p channel MOS transistor, adjacent ones of said first n type regions and one of said second common gate electrodes disposed between said adjacent first n type regions constitute a first n channel MOS transistor, and adjacent ones of said second n type regions and said one of said second common gate electrodes constitute a second n channel MOS transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-08-16 | 1992-02-15 | 1992-08-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-08-16 | 1996-02-15 | 1996-08-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-08-16 | 2000-02-15 | 2000-08-16 | $7700.00 | Window Closed / Lapsed |