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US4763248A
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Microcomputer with a detecting function of a memory access error
Assignee: NEC Electronics Corp
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Filing: 1984-08-27
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Granted: 1988-08-09
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Expires: 2004-08-27
Abstract
Abstract A microcomputer with a stored program memory has a detecting circuit for detecting a memory access error by which an unrequired code is read out of the memory. The detecting circuit receives a read-out instruction code from the memory according to memory access operation in parallel with a receiving operation of an instruction decoder and detects a read-out code from a memory location in which a program to be processed is not written. Undesired processing can be immediately inhibited and the operator can easily find the occurrence of the memory access error.
Inventors
- 👤 Yoshitaka Kitada
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 06:46
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/0703; G06F11/0751; G06F11/0763; G06F11/30; G06F11/32; G06F11/324; G06F11/327
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
214 words
A microcomputer comprising: a memory having a plurality of memory locations, each memory location consisting of a plurality of bits, a plurality of program instruction codes containing both "0" and "1" bits being stored in a portion of said memory locations and the remaining portion of said memory locations storing a predetermined code wherein said predetermined code is not a program instruction code; a memory access means coupled to said memory for applying an address to said memory to select one of said plurality of memory locations for reading a plurality of bits of the selected memory location; an instruction decoding means coupled to said memory for decoding the plurality of bits of the selected memory location read out of said memory; a processing means coupled to said instruction decoding means for executing a processing operation in response to an output of said instruction decoding means; a detecting means coupled to said memory for receiving the plurality of bits of the selected memory location read out of said memory to detect said predetermined code for generating a detection signal which indicates that a memory access error has occurred when the predetermined code is detected; and a control means coupled to said detecting means for starting an error operation in response to said detection signal.
Claim 2
Dependent Claim
214 words
A microcomputer comprising: a memory having a plurality of memory locations, each memory location consisting of a plurality of bits, a plurality of program instruction codes containing both "0" and "1" bits being stored in a portion of said memory locations and the remaining portion of said memory locations storing a predetermined code wherein said predetermined code is not a program instruction code; a memory access means coupled to said memory for applying an address to said memory to select one of said plurality of memory locations for reading a plurality of bits of the selected memory location; an instruction decoding means coupled to said memory for decoding the plurality of bits of the selected memory location read out of said memory; a processing means coupled to said instruction decoding means for executing a processing operation in response to an output of said instruction decoding means; a detecting means coupled to said memory for receiving the plurality of bits of the selected memory location read out of said memory to detect said predetermined code for generating a detection signal which indicates that a memory access error has occurred when the predetermined code is detected; and a control means coupled to said detecting means for starting an error operation in response to said detection signal.
Claim 3
Dependent Claim
41 words
A microcomputer as claimed in claim 1, in which said control means is coupled to said processing means and applies a stop signal to said processing means for stopping an operation of said processing means when said detection signal is generated.
Claim 4
Dependent Claim
42 words
A microcomputer as claimed in claim 1, in which said control means is coupled to said memory access means and applies a hold signal to said memory access means for holding said address of said selected memory location storing said predetermined code.
Claim 5
Dependent Claim
26 words
A microcomputer as claimed in claim 1, in which said control means outputs an error display signal to indicate a memory access error to an operator.
Claim 6
Dependent Claim
14 words
A microcomputer as recited in claim 1, wherein said predetermined code is all 1's.
Claim 7
Dependent Claim
14 words
A microcomputer as recited in claim 1, wherein said predetermined code is all 0's.
Claim 8
Dependent Claim
179 words
A microcomputer comprising: a memory having an instruction code area wherein a plurality of instruction codes are stored and a non-instruction code area wherein a code or codes different from the instruction codes, namely, non-instruction codes, are stored, a memory access circuit coupled to said memory and reading a code out of said memory by applying an address to said memory, a detecting circuit coupled to said memory and detecting whether the code read out of said memory is an instruction code or a non-instruction code, said detecting circuit generating a detection signal when the code is the non-instruction code, said detection signal indicating a memory access error which occurs when said memory access circuit accesses said non-instruction code, an instruction decoder coupled to said memory for decoding the code read-out from said memory, a processing circuit coupled to said instruction decoder for executing a processing operation in response to an output of said instruction decoder, and a control circuit coupled to said detecting circuit for stopping an operation of said processing circuit in response to said detection signal.
Claim 9
Dependent Claim
179 words
A microcomputer comprising: a memory having an instruction code area wherein a plurality of instruction codes are stored and a non-instruction code area wherein a code or codes different from the instruction codes, namely, non-instruction codes, are stored, a memory access circuit coupled to said memory and reading a code out of said memory by applying an address to said memory, a detecting circuit coupled to said memory and detecting whether the code read out of said memory is an instruction code or a non-instruction code, said detecting circuit generating a detection signal when the code is the non-instruction code, said detection signal indicating a memory access error which occurs when said memory access circuit accesses said non-instruction code, an instruction decoder coupled to said memory for decoding the code read-out from said memory, a processing circuit coupled to said instruction decoder for executing a processing operation in response to an output of said instruction decoder, and a control circuit coupled to said detecting circuit for stopping an operation of said processing circuit in response to said detection signal.
Claim 10
Dependent Claim
20 words
A microcomputer as claimed in claim 7, in which said non-instruction code consists of a plurality of the same bits.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-08-09 | 1992-02-08 | 1992-08-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-08-09 | 1996-02-08 | 1996-08-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-08-09 | 2000-02-08 | 2000-08-09 | $7700.00 | Window Closed / Lapsed |