US4761783A
Expired / Lapsed
US
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Apparatus and method for reporting occurrences of errors in signals stored in a data processor
Assignee: Fujitsu IT Holdings Inc
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Filing: 1986-10-17
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Granted: 1988-08-02
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Expires: 2006-10-17
Abstract
Abstract The present invention provides an apparatus for reporting errors in data stored in a memory apparatus of a data processor, comprising: first circuitry for storing multiple digital first signals; second circuitry for storing the multiple digital first signals and adapted for storing at least one digital second signal; third circuitry for transmitting the multiple digital first signals substantially from the first circuitry to the second circuitry; fourth circuitry for providing the at least one digital second signal, in the course of the transmitting of the first signals by the third circuitry, in response to an occurrence of one or more errors in one or more of the multiple digital first signals; fifth circuitry for transmitting the multiple digital first signals substantially from the second circuitry to the first means; and sixth circuitry adapted for receiving the at least one digital second signal in the course of the transmitting of the multiple digital first signals by the fifth circuitry and for providing at least one third signal in response to an occurrence of the at least one digital second signal.
Inventors
- 👤 Harold F. Christensen
- 👤 Joseph A. Petolino, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 05:27
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/0703; G06F11/0766; G06F11/0772; G06F11/0706; G06F11/073; G06F11/08; G06F11/10; G06F12/00
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
230 words
An apparatus for reporting errors in data stored in a memory apparatus of a data processor, comprising: first means for storing multiple digital first signals; second means for storing the multiple digital first signals and adapted for storing at least one digital second signal; third means for transmitting the multiple digital first signals substantially from the first means to said second means; fourth means, for testing, in the course of the transmitting of the first signals by said third means, for an occurrence of one or more errors in the multiple first signals and for providing at least one digital second signal in response to a detecting of an occurence; fifth means for transmitting the multiple first signals substantially from said second means to said first means; sixth means for testing, in the course of the transmitting of the multiple first signals by said fifth means, for an occurrence in said second means of one or more errors in a first set of signals including the multiple first signals, and the at least one second signal; and seventh means for correcting single bit errors detected by the sixth means in the first set of signals. eight means for providing at least one third signal in response to the at least one digital second signal in the course of the transmitting of the multiple digital first signals by said fifth means.
Claim 2
Independent Claim
230 words
An apparatus for reporting errors in data stored in a memory apparatus of a data processor, comprising: first means for storing multiple digital first signals; second means for storing the multiple digital first signals and adapted for storing at least one digital second signal; third means for transmitting the multiple digital first signals substantially from the first means to said second means; fourth means, for testing, in the course of the transmitting of the first signals by said third means, for an occurrence of one or more errors in the multiple first signals and for providing at least one digital second signal in response to a detecting of an occurence; fifth means for transmitting the multiple first signals substantially from said second means to said first means; sixth means for testing, in the course of the transmitting of the multiple first signals by said fifth means, for an occurrence in said second means of one or more errors in a first set of signals including the multiple first signals, and the at least one second signal; and seventh means for correcting single bit errors detected by the sixth means in the first set of signals. eight means for providing at least one third signal in response to the at least one digital second signal in the course of the transmitting of the multiple digital first signals by said fifth means.
Claim 3
Dependent Claim
13 words
The apparatus of claim 1 wherein said first means comprises a cache memory.
Claim 4
Dependent Claim
14 words
The apparatus of claim 1 wherein said second means comprises a main storage unit.
Claim 5
Dependent Claim
61 words
The apparatus of claim 1 wherein said fourth means includes: first means for applying at least one first parity signal to said multiple digital first signals; and first checking means for receiving said multiple digital first signals and said at least one first parity signal and for detecting an occurrence of one or more errors in said multiple digital first signals.
Claim 6
Dependent Claim
30 words
The apparatus of claim 1 wherein said fourth means includes: means for testing for an occurrence in said first means of one or more errors in said multiple first signals.
Claim 7
Dependent Claim
34 words
The apparatus of claim 1 and further comprising: means for receiving said digital first signals transmitted by said third means and for delaying a provision of said digital first signals to said second means.
Claim 8
Dependent Claim
40 words
The apparatus of claim 6 wherein said means for receiving and delaying is adapted for receiving said at least one digital second signal and for delaying a provision of said at least one digital second signal to said second means.
Claim 9
Dependent Claim
51 words
The apparatus of claim 1 wherein said sixth means further comprises: means adapted for receiving from said second means the multiple first signals and the at least one second signal and for generating a syndrome comprising a collection of respective binary signals each individually taking on either of two binary states.
Claim 10
Dependent Claim
37 words
The apparatus of claim 1 and further comprising: ninth means for providing at least one fourth signal in response to a detection by said sixth means of multiple occurrences of errors in the first set of signals.
Claim 11
Independent Claim
240 words
A method for reporting an occurrence, in a memory apparatus of a data processor system, of one or more errors in multiple digital first signals transmitted between a first means for storing said signals and a second means for storing said signals, which comprises the following steps: storing the multiple first signals in the first means; transmitting the multiple first signals from the first means to the second means; in the course of said step of transmitting the first signals from the first means to the second means, testing for occurrences of one or more errors in the multiple first signals; providing at least one digital second signal in response to a detection of an occurrence of one or more errors in the multiple first signals; storing the multiple first signals and the at least one second signal in the second means; transmitting the multiple first signals from the second means to the first means; and testing for occurrences, occurring in the course of said second step of storing, of one or more errors in a first set of signals including the multiple first signals and the at least one second signal; correcting single bit errors detected in the first set of signals; and providing at least one third signal, in the course of said step of transmitting the multiple first signals from the second means to the first means, in response to the at least one digital second signal;
Claim 12
Independent Claim
240 words
A method for reporting an occurrence, in a memory apparatus of a data processor system, of one or more errors in multiple digital first signals transmitted between a first means for storing said signals and a second means for storing said signals, which comprises the following steps: storing the multiple first signals in the first means; transmitting the multiple first signals from the first means to the second means; in the course of said step of transmitting the first signals from the first means to the second means, testing for occurrences of one or more errors in the multiple first signals; providing at least one digital second signal in response to a detection of an occurrence of one or more errors in the multiple first signals; storing the multiple first signals and the at least one second signal in the second means; transmitting the multiple first signals from the second means to the first means; and testing for occurrences, occurring in the course of said second step of storing, of one or more errors in a first set of signals including the multiple first signals and the at least one second signal; correcting single bit errors detected in the first set of signals; and providing at least one third signal, in the course of said step of transmitting the multiple first signals from the second means to the first means, in response to the at least one digital second signal;
Claim 13
Dependent Claim
47 words
The method of claim 10 and further comprising the step of: providing at least one fourth signal in response to a detection of occurrences of multiple errors in the first set of signals, the detected multiple errors occurring in the course of said second step of storing.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-08-02 | 1992-02-01 | 1992-08-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-08-02 | 1996-02-01 | 1996-08-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-08-02 | 2000-02-01 | 2000-08-02 | $7700.00 | Window Closed / Lapsed |