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Patent US4761759A successfully refreshed from Google Patents.
US4761759A
Expired / Lapsed
US
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Absolute value comparator for differences
Assignee: Mitsubishi Electric Corp
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Filing: 1986-03-17
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Granted: 1988-08-02
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Expires: 2006-03-17
Abstract
Abstract An absolute value comparator for differences comprising a first subtracter (1a) and a second subtracter (1b) each of which performs subtraction of n-bit digital values, a controller (8) for receiving most significant bit (MSB) carry output (g) from the first subtracter (1a) and MSB carry output (h) from the second subtracter (1b) to decide coincidence/incoincidence of the said signs as well as the sign of the output (f) from the second subtracter (1b), a first selecter (10a) for selectively passing either the output (e) from the first subtracter (1a) or a digital value obtained by inverting all bits of the output (e) responsive to a sign coincidence/incoincidence detecting signal (t) from the controller (8), a full adder (7) for receiving the sign coincidence/incoincidence detecting signal (u) from the controller (8) in its carry input terminal for the LSB stage to perform addition of output (q) from the least significant bit first selecter (10a) and the output (f) from the second subtracter (1b) to output a signal (r) indicating the sign of the result of calculation and a second selecter (10b) for selectively passing either the output (r) from the full adder (7) or an inverted signal thereof responsive to the sign detecting signal (v) from the controller (18) for the output (f) from the second subtracter (1b).
Inventors
- 👤 Shinichi Nakagawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 16:22
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/02; G06F7/026
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
310 words
An absolute value comparator for performing comparison of the absolute value of difference between first and second n-bit digital values and that of difference between third and fourth n-bit digital values, said comparator comprising: a first substractor for performing subtraction of said first and second digital values thereby to supply the result of subtraction and a first sign indicating signal indicating the sign of the result of subtraction; a second subtractor for performing subtraction of said third and fourth digital values to supply the result of subtraction and a second sign indicating signal indicating the sign of the result of subtraction; controller means for receiving said first sign indicating signal from said first subtractor and said second sign indicating signal from said second subtractor to decide the coincidence or incoincidence of the signs indicated by the same thereby to output sign identifying signals, said sign identifying signals indicating the result of decision; said absolute value comparator further comprising: operating means for performing, in response to said sign identifying signals, operation on either subtraction of said result of subtraction in said first subtractor and said result of subtraction in said second subtractor or addition of said result of subtraction in said first subtractor and said result of subtraction in said second subtractor to output a third sign indicating signal indicating the sign of the result of operation on either the subtraction or addition; controller means for receiving said second sign indicating signal from said second subtractor to detect the sign indicated by said second sign indicating signal thereby to output a fourth sign indicating signal; and selecting means for receiving said third sign indicating signal from said operating means to selectively pass either said third sign indicating signal or an inverted signal of said third sign indicating signal in response to said fourth sign indicating signal from said sign detecting means.
Claim 2
Dependent Claim
310 words
An absolute value comparator for performing comparison of the absolute value of difference between first and second n-bit digital values and that of difference between third and fourth n-bit digital values, said comparator comprising: a first substractor for performing subtraction of said first and second digital values thereby to supply the result of subtraction and a first sign indicating signal indicating the sign of the result of subtraction; a second subtractor for performing subtraction of said third and fourth digital values to supply the result of subtraction and a second sign indicating signal indicating the sign of the result of subtraction; controller means for receiving said first sign indicating signal from said first subtractor and said second sign indicating signal from said second subtractor to decide the coincidence or incoincidence of the signs indicated by the same thereby to output sign identifying signals, said sign identifying signals indicating the result of decision; said absolute value comparator further comprising: operating means for performing, in response to said sign identifying signals, operation on either subtraction of said result of subtraction in said first subtractor and said result of subtraction in said second subtractor or addition of said result of subtraction in said first subtractor and said result of subtraction in said second subtractor to output a third sign indicating signal indicating the sign of the result of operation on either the subtraction or addition; controller means for receiving said second sign indicating signal from said second subtractor to detect the sign indicated by said second sign indicating signal thereby to output a fourth sign indicating signal; and selecting means for receiving said third sign indicating signal from said operating means to selectively pass either said third sign indicating signal or an inverted signal of said third sign indicating signal in response to said fourth sign indicating signal from said sign detecting means.
Claim 3
Dependent Claim
84 words
An absolute value comparator for differences in accordance with claim 1, wherein said operating means perform subtraction of said result of subtraction in said first subtractor from said result of subtraction in said second subtractor in response to a sign coincidence detecting signal from said controller means; and said operating means further performing addition of said result of subtraction in said first substractor and said result of subtraction in said second substractor in response to a sign incoincidence detecting signal from said controller means.
Claim 4
Dependent Claim
54 words
An absolute value comparator for differences in accordance with claim 2, wherein said selecting means passes said output from said operating means when said fourth sign indicating signal indicates negative; and said selecting means further passing said inverted signal of said output from said operating means when said fourth sign indicating signal indicates positive.
Claim 5
Dependent Claim
170 words
An absolute value comparator for differences in accordance with claim 1, wherein said sign indicating signals from said controller means includes a first sign identifying signal and a second sign identifying signal of a binary level; said operating means comprising: second selecting means for receiving said result of subtraction in said first subtractor to selectively pass either said result of subtraction or a bit-inverted value obtained by inverting all bits of said result of subtraction in response to said first sign identifying signal; said operating means further comprising: full adder means for receiving both a digital value signal from said second selecting means and said result of subtraction in said second subtractor and said second sign identifying signal in the carry input terminal of the least significant bit stage thereof; said full adder means performing addition of said digital value signal from said second selecting means and said result of subtraction in said second subtractor; and said full adder means outputting a carry of the most significant bit stage thereof.
Claim 6
Dependent Claim
45 words
An absolute value comparator for differences in accordance with claim 1, wherein said first to fourth n-bit digital values are binary-coded digital values, said results of subtraction in said first and second subtractors being (n+1)-bit digital values including carries at the most significant bit stages.
Claim 7
Dependent Claim
46 words
An absolute value comparator for differences in accordance with claim 1, wherein said first to fourth n-bit digital values are offset binary-coded digital values, said results of subtraction in said first and second subtractors being (n+1)-bit digital values including carries at the most significant bit stages.
Claim 8
Dependent Claim
39 words
An absolute value comparator for differences in accordance with claim 1, wherein said first to fourth n-bit digital values are two's complement coded digital values, said results of subtraction in said first and second subtractors being n-bit digital values.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-08-02 | 1992-02-01 | 1992-08-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-08-02 | 1996-02-01 | 1996-08-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-08-02 | 2000-02-01 | 2000-08-02 | $7700.00 | Window Closed / Lapsed |