← Back to Patent Explorer
US4761677A Expired / Lapsed US ⏱️ 0.0 years remaining

Semiconductor device having new conductive interconnection structure and method for manufacturing the same

Assignee: Fujitsu Ltd
•
Filing: 1987-01-22
•
Granted: 1988-08-02
•
Expires: 2007-01-22
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A reliable multilevel interconnection structure is attained by using polyacetylene layers. Nondoped polyacetylene is dielectric but is conductive when it is doped with an impurity such as AsF 5 , which makes it possible to eliminate the necessity of opening a contact hole or through hole in an insulating layer in a process for manufacturing a multilevel interconnection structure so that a disconnection and/or short circuit does not occur due to the evenness of the layers even if the layer of numbers is increased.

Inventors

  • 👤 Nobuo Sasaki

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 21:39
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/60; H10P14/68; H10P14/683; H10K; H10K85/00; H10K85/10; H10K85/141; H10K85/143; H10W; H10W20/00; H10W20/01; H10W20/40; H10W20/41; H10W20/44; H10W20/4473

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 89 words
A semiconductor device comprising: a substrate; wiring layers formed on said substrate; a conductive region formed in said substrate; a first polyacetylene layer formed on said conductive region, said first polyacetylene layer exhibiting insulating properties and having a first doped region, said first doped region being conductive and being electrically connected to said conductive region; and a second polyacetylene layer formed directly on said first polyacetylene layer and including a second doped region electrically connected to said conductive region below said first polyacetylene layer through said first doped region.
Claim 2
Dependent Claim 89 words
A semiconductor device comprising: a substrate; wiring layers formed on said substrate; a conductive region formed in said substrate; a first polyacetylene layer formed on said conductive region, said first polyacetylene layer exhibiting insulating properties and having a first doped region, said first doped region being conductive and being electrically connected to said conductive region; and a second polyacetylene layer formed directly on said first polyacetylene layer and including a second doped region electrically connected to said conductive region below said first polyacetylene layer through said first doped region.
Claim 3
Dependent Claim 22 words
A semiconductor device according to claim 1, wherein said conductive region is a diffused region formed in a portion of said substrate.
Claim 4
Dependent Claim 38 words
A semiconductor device according to claim 1, further comprising a third polyacetylene layer formed under said first polyacetylene layer having a third doped region, wherein said conductive region is the third doped region of said third polyacetylene layer.

References Cited (Backward Citations)

US3634927A Cited
US3967371A Cited
US3766445A Cited
US3806778A Cited
US4045302A Cited
US4199778A Cited
US4204216A Cited
US4222903A Cited
US4269738A Cited
EP0021818A1 Cited
EP0022271A1 Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1991-08-02 1992-02-01 1992-08-02 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1995-08-02 1996-02-01 1996-08-02 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1999-08-02 2000-02-01 2000-08-02 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag