Clock scheme for VLSI systems

Claim 2

An integrated circuit comprising: an input pad connected to receive a first external clock signal; input clock generator means responsive to said first clock signal for generating an internal system clock signal; means for selectively enabling or disabling of said input clock generator means; input/output pad connected to receive said internal system clock signal and to provide said internal system clock signal to other integrated circuits; internal clock generator means being responsive to said internal system clock signal for generating a first internal phase clock signal and a second internal phase clock signal which is complementary to the first internal phase clock signal when said input clock generator means is enabled; said input/output pad being further connected to receive a second external system clock signal when said input clock generator means is disabled; and said internal clock generator means being responsive to said second external system clock signal for generating said first and second internal phase clock signals when said input clock generator means is disabled.

Claim 3

An integrated circuit as claimed in claim 1, wherein said input clock generator means comprises an input clock generator circuit having an input and an output and a clock generator driver circuit having an input and an output.

Claim 4

An integrated circuit as claimed in claim 2, wherein said input clock generator circuit has its input connected to said input pad, and wherein said clock generator driver circuit has its input connected to the output of said input clock generator circuit and has its output connected to said input/output pad.

Claim 5

An integrated circuit as claimed in claim 1, wherein said internal clock generator means comprises an internal clock generator circuit.

Claim 6

An integrated circuit as claimed in claim 1, wherein said means for selectively enabling or disabling of said input clock generator means comprises a clock output enable circuit.

Claim 7

An integrated circuit as claimed in claim 1, wherein said first external clock signal is a TTL level clock signal.

Claim 8

An integrated circuit as claimed in claim 6, wherein said internal clock signal is a CMOS level system clock signal.

Claim 9

An integrated circuit as claimed in claim 7, wherein said second external clock signal is a common CMOS level system clock signal.

Claim 10

An integrated circuit as claimed in claim 1, further comprising timing circuit means responsive to either said internal clock signal or said second external clock signal.

Claim 11

An integrated circuit comprising: an input pad connected to receive an external TTL level clock signal; input clock generator means responsive to said TTL level clock signal for generating an internal CMOS level system clock signal; means for selectively enabling or disabling of said input clock generator means; input/output pad connected to receive said internal CMOS level system clock signal and to provide said internal system clock signal to other integrated circuits; internal clock generator means being responsive to said internal CMOS level system clock signal for generating a first internal CMOS level phase clock signal and a second internal CMOS level phase clock signal which is complementary to the first internal CMOS level phase clock signal when said input clock generator means is enabled; said input/output pad being further connected to receive a common external CMOS level system clock signal when said input clock generator means is disabled; and said internal clock generator means being responsive to said common external CMOS level system clock signal for generating said first and second internal CMOS level phase clock signals when said input clock generator means is disabled.

Claim 12

An integrated circuit comprising: an input pad connected to receive an external TTL level clock signal; input clock generator means responsive to said TTL level clock signal for generating an internal CMOS level system clock signal; means for selectively enabling or disabling of said input clock generator means; input/output pad connected to receive said internal CMOS level system clock signal and to provide said internal system clock signal to other integrated circuits; internal clock generator means being responsive to said internal CMOS level system clock signal for generating a first internal CMOS level phase clock signal and a second internal CMOS level phase clock signal which is complementary to the first internal CMOS level phase clock signal when said input clock generator means is enabled; said input/output pad being further connected to receive a common external CMOS level system clock signal when said input clock generator means is disabled; and said internal clock generator means being responsive to said common external CMOS level system clock signal for generating said first and second internal CMOS level phase clock signals when said input clock generator means is disabled.

Claim 13

An integrated circuit as claimed in claim 10, further comprising a plurality of integrated circuits connected in a self-clocking configuration so that one of the integrated circuits is responsive to the TTL level clock signal for producing the internal CMOS level system clock signal and the remaining integrated circuits are responsive to the internal CMOS level system clock signal.

Claim 14

An integrated circuit as claimed in claim 10, further comprising a plurality of integrated circuits connected in a common external clock configuration so that each of said plurality of integrated circuits is responsive to the common external CMOS level system clock signal.