Rewritable semiconductor memory device having a decoding inhibit function

Claim 2

A semiconductor memory device comprising: a memory matrix constituted by a plurality of rewritable memory elements which are arranged in m rows and n columns wherein m and n are positive integers, each of said memory elements being selected by a selection signal in accordance with signals on address lines associated with said memory matrix; means for temporarily applying state setting external signals to a plurality of said address lines with a predetermined time interval; state setting internal signal generating means for converting said state setting external signals applied to respective address lines into a selected one of a first state setting internal signal and a second state setting internal signal, corresponding to first and second modes, said first state setting internal signal having a different phase from said second state setting internal signal; a column selection decoder controlled by a chip enable signal for producing the selection signal; and a column selection decoding function control means supplied with the selected one of said first and second state setting internal signals and said chip enable signal for controlling the decoding function of said column selection decoder such that said column selection decoder generates the selection signal when the selected one of said first and second state setting internal signals has a first logical level and does not generate the selection signal when the selected one of said first and second state setting internal signals has a second logical level.

Claim 3

The semiconductor memory device according to claim 1 wherein said state setting internal signal generating means comprises first and second set-reset type flip-flop circuits having set input terminals respectively connected to said address lines through input buffer circuits having high threshold values; circuit means for supplying a common reset signal to reset input terminals of said flip-flop circuits; first and second NOR gate circuits having one input terminal respectively connected to receive Q outputs of said flip-flop circuits; an input buffer circuit having an ordinary threshold value and connected between one of said address lines and a second input terminal of said first NOR gate circuit; an inverter connected between an output terminal of said ordinary threshold value input buffer circuit and a second input terminal of said second NOR gate circuit; a third NOR gate circuit receiving the outputs of said first and second NOR gate circuits; and an inverter for inverting an output signal of said third NOR gate circuit.

Claim 4

The semiconductor memory device according to claim 1 wherein said column selection decoding function control means comprises a NOR gate circuit which receives said chip enable signal and one of said first and second state setting internal signals, and an inverter for inverting an output of said NOR gate circuit and for supplying the output of said inverter to said column selection decoder.

Claim 5

A semiconductor memory device comprising: a memory matrix constituted by a plurality of rewritable memory elements which are arranged in m rows and n columns wherein m and n are positive integers; means for temporarily applying state setting external signals to a pair of address lines with a predetermined time interval; state setting internal signal generating means for converting said state setting external signals applied to respective address lines into a selected one of a first state setting internal signal and a second state setting internal signal, corresponding to first and second modes, said first state setting internal signal having a different phase from said second state setting internal signal, said state setting internal signal generating means comprising first and second set-reset type flip-flop circuits having set input terminals respectively connected to said address lines through input buffer circuits having high threshold values, circuit means for supplying a common reset signal to reset input terminals of said flip-flop circuits, first and second NOR gate circuits having one input terminal connected to receive Q outputs of said flip-flop circuits, an input buffer circuit having an ordinary threshold value and connected between one of said address lines and a second input terminal of said first NOR gate circuit, an inverter connected between an output terminal of said ordinary threshold value input buffer circuit and a second input terminal of said second NOR gate circuit, a third NOR gate circuit receiving outputs of said first and second NOR gate circuits, and an inverter for inverting an output signal of said third NOR gate circuit; a column selection decoder controlled by a chip enable signal for producing the selection signal; and a column selection decoding function control means supplied with one of said first and second state setting internal signals and said chip enable signal for controlling the decoding function of said column selection decoder in said first and second modes such that said column selection decoder generates the selection signal having a same phase as that of the state setting external signal supplied to one of said address lines when said first state setting internal signal is supplied thereto, and generates the selection signal having an opposite phase to that of the state setting external signal supplied to one of said address lines when said second state setting internal signal is supplied thereto.

Claim 6

A semiconductor memory device comprising: a memory matrix constituted by a plurality of rewritable memory elements which are arranged in m rows and n columns wherein m and n are positive integers; means for temporarily applying state setting external signals to a pair of address lines with a predetermined time interval; state setting internal signal generating means for converting said state setting external signals applied to respective address lines into a selected one of a first state setting internal signal and a second state setting internal signal, corresponding to first and second modes, said first state setting internal signal having a different phase from said second state setting internal signal, said state setting internal signal generating means comprising first and second set-reset type flip-flop circuits having set input terminals respectively connected to said address lines through input buffer circuits having high threshold values, circuit means for supplying a common reset signal to reset input terminals of said flip-flop circuits, first and second NOR gate circuits having one input terminal connected to receive Q outputs of said flip-flop circuits, an input buffer circuit having an ordinary threshold value and connected between one of said address lines and a second input terminal of said first NOR gate circuit, an inverter connected between an output terminal of said ordinary threshold value input buffer circuit and a second input terminal of said second NOR gate circuit, a third NOR gate circuit receiving outputs of said first and second NOR gate circuits, and an inverter for inverting an output signal of said third NOR gate circuit; a column selection decoder controlled by a chip enable signal for producing the selection signal; and a column selection decoding function control means supplied with one of said first and second state setting internal signals and said chip enable signal for controlling the decoding function of said column selection decoder in said first and second modes such that said column selection decoder generates the selection signal having a same phase as that of the state setting external signal supplied to one of said address lines when said first state setting internal signal is supplied thereto, and generates the selection signal having an opposite phase to that of the state setting external signal supplied to one of said address lines when said second state setting internal signal is supplied thereto.