Semiconductor memory device having diode matrix type decoder and redundancy configuration

Claim 1

A bipolar-transistor type semiconductor memory device having a redundancy configuration, comprising: a memory cell array; a first redundancy memory cell array; a first address buffer circuit including a predetermined number of first emitter-coupled logic gates having output terminals, a predetermined number of first input address signals being input to each of said logic gates, each of said logic gates comparing a voltage level of the corresponding first input address signal with a voltage level of a reference signal; a group of first decoder lines, each of said first decoder lines, respectively, operatively connected to a predetermined one of said output terminals; a first comparator circuit, operatively connected to said address buffer circuit, for detecting whether or not each of said first input address signals coincides with an address signal corresponding to a defective memory cell and outputting a first selection signal in accordance with a coincidence between said first input address signal and the address signal corresponding to said defective memory cell; a switching circuit, having an output terminal and operatively connected to said first comparator circuit, for comparing a voltage level of said first selection signal with a voltage level of the reference signal; a second decoder line operatively connected to said output terminal of said switching circuit; and a predetermined number of first diode groups operatively connected to said memory cell array each of said first diode groups comprising a predetermined number of first diodes and a second diode, said first diodes connected to said first decoder lines and said second diode connected to said second decoder line, the conductive state of each of said first diodes being determined by a voltage level on a predetermined one of said first decoder lines, the conductive state of said second diode being determined by a voltage level on said second decoder line, said memory cell array being selected by said predetermined number of first diode groups in accordance with said first input address signals when said first comparator circuit does not output said first selection signal, said first redundancy memory cell array being selected when said first comparator circuit does output said first selection signal, making said second diode conductive.