Patent US4757473A successfully refreshed from Google Patents.
US4757473A
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US
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Memory circuit
Assignee: Hitachi Ltd
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Filing: 1986-05-21
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Granted: 1988-07-12
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Expires: 2006-05-21
Abstract
Abstract A dual-port memory circuit comprises a random port having a memory cell array randomly accessable and a serial port serially readable or writable from/to the memory cell array. In the memory circuit, two modes are provided to the serial port, and when a first mode is designated, the data are consecutively read or written a plurality of bits at a time, and when a second mode is designated, the data are consecutively read or written one bit at a time. High speed read/write operation is attained by designating the mode to allow parallel input/output. For an application which does not require high speed operation, the number of components to be externally added to the memory circuit can be reduced.
Inventors
- 👤 Ryoichi Kurihara
- 👤 Hiroaki Aotsu
- 👤 Toshihiko Ogura
- 👤 Koichi Kimura
- 👤 Tadashi Kyoda
- 👤 Hiromichi Enomoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 16:30
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C7/00; G11C7/10; G11C7/1075; G06; G06F; G06F12/00; G06F12/02; G06F12/06; G11C8/00; G11C8/16
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
116 words
A memory circuit comprising: a memory cell array including means for reading out data bits contained in a row of the array in parallel; a data latch circuit for holding the read data bits; a signal line for applying a control signal to indicate one of two modes to said data latch circuit; and a control circuit connected to said signal line for causing said data latch circuit to selectively output a plurality of said data bits in parallel when said control signal incidates a first mode and for causing said data latch circuit to selectively output said plurality of data bits serially one bit at a time when said control signal indicates a second mode.
Claim 2
Dependent Claim
116 words
A memory circuit comprising: a memory cell array including means for reading out data bits contained in a row of the array in parallel; a data latch circuit for holding the read data bits; a signal line for applying a control signal to indicate one of two modes to said data latch circuit; and a control circuit connected to said signal line for causing said data latch circuit to selectively output a plurality of said data bits in parallel when said control signal incidates a first mode and for causing said data latch circuit to selectively output said plurality of data bits serially one bit at a time when said control signal indicates a second mode.
Claim 3
Dependent Claim
96 words
A memory circuit according to claim 1 wherein said control circuit includes a selection circuit for outputting the plurality of data bits in parallel by selecting the plurality of bit positions of said data latch circuit, and a shift register connected to said selector circuit for outputting the data bits selected in parallel by said selection circuit as they are when said control signal line indicates the first mode and for converting the data bits selected by said selection circuit to output the data bits bit by bit when said signal line indicates the second mode.
Claim 4
Dependent Claim
51 words
A memory circuit according to claim 1 further comprising: a code latch for temporarily storing an operation code externally supplied thereto; a decoder for decoding the contents of said code latch; and a mode latch for holding the output of said decoder; said signal line being connected to said mode latch.
Claim 5
Dependent Claim
120 words
A memory circuit comprising: a memory cell array including means for reading out data bits controlled in a row of the array in parallel; a data latch circuit for holding the data bits to be written into said memory cell array; a signal line for applying a signal to indicate one of first and second modes to said data latch circuit; and a control circuit connected to said signal line for selecting a plurality of data bits to be supplied in parallel to said data latch circuit when said signal line indicates the first mode and for selecting data bits to be supplied serially bit by bit to said data latch circuit when said signal line indicates the second mode.
Claim 6
Dependent Claim
120 words
A memory circuit comprising: a memory cell array including means for reading out data bits controlled in a row of the array in parallel; a data latch circuit for holding the data bits to be written into said memory cell array; a signal line for applying a signal to indicate one of first and second modes to said data latch circuit; and a control circuit connected to said signal line for selecting a plurality of data bits to be supplied in parallel to said data latch circuit when said signal line indicates the first mode and for selecting data bits to be supplied serially bit by bit to said data latch circuit when said signal line indicates the second mode.
Claim 7
Dependent Claim
90 words
A memory circuit according to claim 4 wherein said control circuit includes a selection circuit for supplying the plurality of data bits in parallel by selecting the plurality of bit positions of said data latch circuit, and a shift register connected to said selection circuit for supplying the data bits to said control selection circuit as they are when said signal indicates the first mode and for converting the data bits to be serially supplied bit by bit to said selection circuit when said control signal indicates the second mode.
Claim 8
Dependent Claim
51 words
A memory circuit according to claim 4 further comprising: a code latch for temporarily storing an operation code externally supplied thereto; a decoder for decoding the contents of said code latch; and a mode latch for holding the output of said decoder; said signal line being connected to said mode latch.
Claim 9
Dependent Claim
116 words
A memory circuit comprising: a memory cell array including means for reading out data bits contained in a row of the array in parallel; a data latch circuit for holding data bits to be read-out from said memory cell array; a signal line for applying a control signal to indicate one of first and second modes and a control circuit connected to said signal line for selecting a plurality of data bits to be outputted in parallel from said data latch circuit when said control signal indicates the first mode and the selecting the data bits to be outputted serially bit by bit from said data latch circuit when said control signal indicates the second mode.
Claim 10
Dependent Claim
116 words
A memory circuit comprising: a memory cell array including means for reading out data bits contained in a row of the array in parallel; a data latch circuit for holding data bits to be read-out from said memory cell array; a signal line for applying a control signal to indicate one of first and second modes and a control circuit connected to said signal line for selecting a plurality of data bits to be outputted in parallel from said data latch circuit when said control signal indicates the first mode and the selecting the data bits to be outputted serially bit by bit from said data latch circuit when said control signal indicates the second mode.
References Cited (Backward Citations)
US4402067A
Cited
US4639890A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-07-12 | 1992-01-11 | 1992-07-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-07-12 | 1996-01-11 | 1996-07-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-07-12 | 2000-01-11 | 2000-07-12 | $7700.00 | Window Closed / Lapsed |