US4757439A
Expired / Lapsed
US
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Memory bus architecture
Assignee: Honeywell Measurex Corp
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Filing: 1987-07-06
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Granted: 1988-07-12
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Expires: 2007-07-06
Abstract
Abstract A memory bus architecture uses a standard unified bus, microprocessor system, and separate memory bus. Access to memory banks coupled to the memory bus may be made by subsystems communicating over the unified bus using the standard protocol of the unified bus, or may be made by the microprocessor using an access protocol method wherein an accessed memory bank generates an acknowledgement signal upon receipt of a READ or WRITE command rather than after the completion of the respective READ or WRITE operation. A further aspect is an Early READ/WRITE circuit that rapidly detects the initiation of a READ or WRITE command by the microprocessor by decoding standard microprocessor status signals in order to generally commence a READ or WRITE operation prior to the time that a normal READ or WRITE operation would be commenced.
Inventors
- 👤 Gene R. Stinson
- 👤 Anna S. Williams
- 👤 Maximilian P. Jedda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 09:33
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4234; G06F13/4243
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
361 words
A microprocessor system comprising: a. a microprocessor having status information output indicative of an impending read or write operation and further generating standard read and write commands; b. a unified standard bus coupled to the microprocessor and to at least one external source of command information, including standard read and write commands; c. a memory bus coupled to the microprocessor; d. a first detection circuit coupled to the microprocessor and to the memory bus for receiving the status information, generating an early command signal in response to the status information and indicative of a read or write operation, and transmitting that early command signal by means of the memory bus prior to the generation of the corresponding standard command; e. an addressable memory, coupled to the memory bus, including means for receiving read and write command signals and means for performing read write operations in response to received read and write command signals, means for generating an acknowledgment signal in response to a received read or write command signal and prior to the completion of the commanded read or write operation, and means for transmitting the acknowledgement signal by means of the memory bus to the microprocessor, whereby the microprocessor, upon receipt of the acknowledgement signal, is enabled to output further status information indicative of a next impending read or write operation; f. a second detection circuit coupled to the microprocessor, the unified standard bus, and the first detection circuit for receiving command information over the unified standard bus indicative of a conflict between the microprocessor and an external source of command information with respect to control of the unified standard bus and for generating a control signal for preventing the first detection circuit from supplying an early command signal to the addressable memory; and g. means to electrically couple the unified standard bus to the memory bus, and wherein, in response to the control signal from the second detection circuit, the addressable memory is enabled to be directly responsive to standard read and write commands from an external source of command information for reading or writing data by means of the memory bus to or from the unified standard bus.
Claim 2
Dependent Claim
361 words
A microprocessor system comprising: a. a microprocessor having status information output indicative of an impending read or write operation and further generating standard read and write commands; b. a unified standard bus coupled to the microprocessor and to at least one external source of command information, including standard read and write commands; c. a memory bus coupled to the microprocessor; d. a first detection circuit coupled to the microprocessor and to the memory bus for receiving the status information, generating an early command signal in response to the status information and indicative of a read or write operation, and transmitting that early command signal by means of the memory bus prior to the generation of the corresponding standard command; e. an addressable memory, coupled to the memory bus, including means for receiving read and write command signals and means for performing read write operations in response to received read and write command signals, means for generating an acknowledgment signal in response to a received read or write command signal and prior to the completion of the commanded read or write operation, and means for transmitting the acknowledgement signal by means of the memory bus to the microprocessor, whereby the microprocessor, upon receipt of the acknowledgement signal, is enabled to output further status information indicative of a next impending read or write operation; f. a second detection circuit coupled to the microprocessor, the unified standard bus, and the first detection circuit for receiving command information over the unified standard bus indicative of a conflict between the microprocessor and an external source of command information with respect to control of the unified standard bus and for generating a control signal for preventing the first detection circuit from supplying an early command signal to the addressable memory; and g. means to electrically couple the unified standard bus to the memory bus, and wherein, in response to the control signal from the second detection circuit, the addressable memory is enabled to be directly responsive to standard read and write commands from an external source of command information for reading or writing data by means of the memory bus to or from the unified standard bus.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-07-12 | 1992-01-11 | 1992-07-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-07-12 | 1996-01-11 | 1996-07-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-07-12 | 2000-01-11 | 2000-07-12 | $7700.00 | Window Closed / Lapsed |