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US4756013A
Expired / Lapsed
US
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Multi-function counter/timer and computer system embodying the same
Assignee: US Philips Corp
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Filing: 1986-04-23
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Granted: 1988-07-05
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Expires: 2006-04-23
Abstract
Abstract A programmable counter/timer is responsive to signals on a data line for producing signals on one or more output lines and includes a counter connected to the data line, a comparator connected to said counter for producing a control signal when said counter reaches a stored preselected value, and a qualification unit connected to the comparator, the qualification unit having a register for storing a logic state. The qualification unit is responsive to the control signal and the stored logic state for generating a signal on selected output lines when the counter reaches the predetermined stored value.
Inventors
- 👤 Evert D. Van Veldhuizen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 16:07
CPC Classifications
G; G06; G06F; G06F15/00; G05; G05B; G05B19/00; G05B19/02; G05B19/04; G05B19/042
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
105 words
A programmable counter/timer responsive to signals on a data line for producing output signals on two or more output lines comprising: a counter connectable to the data line; a comparator unit connected to said counter for producing a control signal when said counter reaches a preselected value; a qualification unit connected to said comparator unit and said two or more output lines, said qualification unit including plural means for storing a plurality of logic states in response to said data line for generating a signal on selected ones of said output lines in response to said control signal when said counter reaches said predetermined value.
Claim 2
Dependent Claim
105 words
A programmable counter/timer responsive to signals on a data line for producing output signals on two or more output lines comprising: a counter connectable to the data line; a comparator unit connected to said counter for producing a control signal when said counter reaches a preselected value; a qualification unit connected to said comparator unit and said two or more output lines, said qualification unit including plural means for storing a plurality of logic states in response to said data line for generating a signal on selected ones of said output lines in response to said control signal when said counter reaches said predetermined value.
Claim 3
Dependent Claim
68 words
The counter/timer of claim 1 wherein said qualification unit comprises a plurality of flip flops and a corresponding plurality of logic gates, each logic gate having a first input connected to an output of one of said plurality of flip flops and a second input connected to the output of said comparator, the outputs of said plurality of logic gates connected to said one or more output lines.
Claim 4
Dependent Claim
11 words
The counter/timer of claim 2 wherein said logic gates comprise AND-gates.
Claim 5
Dependent Claim
25 words
The counter/timer of claim 1 wherein said comparator unit comprises a comparison register connected to said dataline and a comparator connected to said comparison register.
Claim 6
Dependent Claim
38 words
The counter/timer of claim 1 comprising an output register having a plurality of inputs connected to said output lines, the signals on said output lines adapted to set, reset or invert the logic state of said output register.
Claim 7
Dependent Claim
38 words
The counter/timer of claim 2 comprising an output register having a plurality of inputs connected to said output lines, the signals on said output lines adapted to set, reset or invert the logic state of said output register.
Claim 8
Dependent Claim
38 words
The counter/timer of claim 3 comprising an output register having a plurality of inputs connected to said output lines, the signals on said output lines adapted to set, reset or invert the logic state of said output register.
Claim 9
Dependent Claim
38 words
The counter/timer of claim 4 comprising an output register having a plurality of inputs connected to said output lines, the signals on said output lines adapted to set, reset or invert the logic state of said output register.
Claim 10
Dependent Claim
39 words
The counter/timer of claim 8 wherein said output register comprises a plurality of output flip flops adapted to be either set to the 1-state or to the 0-state, or inverted from one logic state to the other logic state.
Claim 11
Dependent Claim
61 words
The counter/timer of claim 8 wherein said output register comprises a plurality of output flip flops, the qualification unit comprises two flip flops for each of said plurality of output flip flops, the combined states thereof adapted to represent four states: no modification, setting to the 1-state, to the 0-state, or to the inverted logic state of the output flip flop.
Claim 12
Dependent Claim
36 words
A counter/timer as claimed in any one of claims 1-10, comprising a second comparator and a second qualification unit connected to said second comparator and responsive to a second control signal generated by said second comparator.
Claim 13
Dependent Claim
20 words
The counter/timer of claim 11 in which said qualification unit and said second qualification unit control the same output lines.
Claim 14
Dependent Claim
20 words
The counter/timer of claim 11 in which said qualification unit and said second qualification unit control the same output register.
Claim 15
Dependent Claim
49 words
The counter/timer of claim 13 wherein said output register comprises a plurality of output flip flops, each of which includes a set input and a reset input, said qualification unit connected to and controlling said set inputs and said second qualification unit connected to and controlling said reset inputs.
Claim 16
Dependent Claim
26 words
The counter/timer of claim 11 in which said output register comprises toggle flip flop means having inputs connected to the output lines of the qualification unit.
Claim 17
Dependent Claim
36 words
The counter/timer of claim 1 further comprising arithmetic and logic means, program memory, a plurality of registers, and input/output register and bus connection means interconnecting said arithmetic and logic means, program memory, registers, and input/output registers.
Claim 18
Dependent Claim
19 words
The apparatus of claim 16 wherein said comparator unit and said qualification unit are connected to said bus means.
Claim 19
Dependent Claim
15 words
The apparatus of claim 17 wherein said input/output register is connected to said qualification unit.
Claim 20
Dependent Claim
17 words
The apparatus of claim 18 wherein said output register comprises additional inputs connected to said bus means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-07-05 | 1992-01-04 | 1992-07-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-07-05 | 1996-01-04 | 1996-07-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-07-05 | 2000-01-04 | 2000-07-05 | $7700.00 | Window Closed / Lapsed |