Buffer memory device controlled by a least recently used method

Claim 1

A buffer memory device comprising: a plurality of memory blocks each including a register and a comparator for comparing the content of said register and the input data and developing a coincidence signal upon the coincidence thereof; and a control circuit responsive to said coincidence signal for controlling the shift of the data within said registers in such a manner that, when a coincidence signal is developed by a comparator of a selective memory block, only the contents of said registers between the first memory block and the selected memory block are shifted, said control circuit comprising; a plurality of transfer gates, a transfer gate being provided between a data input terminal and said register of said first memory block, for shifting said input data to said first memory block, a transfer gate being provided between each two said adjacent memory blocks for shifting said data between said adjacent registers, a plurality of NOR circuits, a NOR circuit being provided in correspondence with each of said memory blocks for turning ON or OFF said transfer gates, and a plurality of NAND circuits, each said NAND circuit being in correspondence with one of said memory blocks for generating a signal for controlling each of said corresponding NOR circuits in response to the said coincidence signal developed by said one of said memory blocks.