Patent US4911488A successfully refreshed from Google Patents.
Patent US4754467A successfully refreshed from Google Patents.
US4754467A
Expired / Lapsed
US
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Digital signal detection with signal buffering and message insertion
Assignee: Motorola Solutions Inc
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Filing: 1987-07-01
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Granted: 1988-06-28
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Expires: 2007-07-01
Abstract
Abstract An improved digital signal detector for indicating the presence of digital data used in a communication system. While attempting to detect valid data, the detector buffers an incoming signal in a first-in, first-out buffer and allows locally generated data, instead of the buffered signal, to be coupled to an output. After detecting valid data, the detector estimates where in the buffer valid data commenced and either releases data from that point or further delays the signal up to the maximum length of the buffer before releasing it to the output. The invention provides high sensitivity and rapid detection, reduces variation in detection time over previous methods, and allows locally generated data to be inserted into the signal path without loss of valid data. The invention would find application in digital systems that require detection at high bit-error-rates without losing valid data and without relying on a particular message format to assist detection or in systems that locally insert preamble sequences for synchronization and control.
Inventors
- 👤 Dean E. Banwart
- 👤 Michael W. Frenzer
- 👤 Thomas J. McClaughry
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 07:08
CPC Classifications
H; H04; H04L; H04L1/00; H04L1/20
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
119 words
A method for detecting the presence of valid data within an incoming signal and for controlling the flow of the incoming signal to an output according to whether valid data is detected, comprising the steps of: buffering the incoming signal for at least the duration of a buffering time and producing a buffered signal; examining the incoming signal to determine whether it constitutes valid data within the buffering time and continuing to examine the incoming signal until it is determined that it constitutes valid data within the buffering time; after which producing an estimate of when during the buffering time the data became valid; and controlling the flow of the buffered signal to the output according to the estimate.
Claim 2
Independent Claim
119 words
A method for detecting the presence of valid data within an incoming signal and for controlling the flow of the incoming signal to an output according to whether valid data is detected, comprising the steps of: buffering the incoming signal for at least the duration of a buffering time and producing a buffered signal; examining the incoming signal to determine whether it constitutes valid data within the buffering time and continuing to examine the incoming signal until it is determined that it constitutes valid data within the buffering time; after which producing an estimate of when during the buffering time the data became valid; and controlling the flow of the buffered signal to the output according to the estimate.
Claim 3
Dependent Claim
33 words
The method of claim 1 including the step of controlling the flow of locally generated signals to the output according to the estimate of when during the buffering time the data became valid.
Claim 4
Independent Claim
158 words
A method for detecting the presence of valid digital data within an incoming digital signal and for controlling the flow of the incoming digital signal to an output according to whether valid digital data is detected, comprising the steps of: producing transition counts that indicate the relative degree of phase lock between the incoming digital signal and a local clock for the bits during successive count intervals; storing an integral number, N, of the most recent transition counts; buffering successive bits of the incoming digital signal during at least N successive count intervals and producing a buffered digital signal; for each successive transition count produced, comparing a sum of the N most recent transition counts to a threshold; and if the sum is at least equal to the threshold, then producing an estimate of the count interval during which data became valid; and controlling the flow of the buffered digital signal to the output according to the estimate.
Claim 5
Independent Claim
158 words
A method for detecting the presence of valid digital data within an incoming digital signal and for controlling the flow of the incoming digital signal to an output according to whether valid digital data is detected, comprising the steps of: producing transition counts that indicate the relative degree of phase lock between the incoming digital signal and a local clock for the bits during successive count intervals; storing an integral number, N, of the most recent transition counts; buffering successive bits of the incoming digital signal during at least N successive count intervals and producing a buffered digital signal; for each successive transition count produced, comparing a sum of the N most recent transition counts to a threshold; and if the sum is at least equal to the threshold, then producing an estimate of the count interval during which data became valid; and controlling the flow of the buffered digital signal to the output according to the estimate.
Claim 6
Dependent Claim
89 words
The method of claim 3 in which the step of producing an estimate of the count interval during which data became valid comprises the steps of comparing the N most recent transition counts and estimating that if the transition counts have approximately equal magnitudes, then valid data began during the earliest of the N most recent count intervals, or that if the transition counts differ significantly, then valid data began during the count interval for which the transition count increased significantly from transition counts stored for earlier count intervals.
Claim 7
Dependent Claim
59 words
The method of claim 3 in which the step of controlling the flow of the buffered digital signal includes the steps of allowing locally generated data to be coupled to the output before detecting the presence of valid data and coupling the buffered digital signal to the output without significant additional delay after detecting the presence of valid data.
Claim 8
Dependent Claim
95 words
The method of claim 3 in which the step of controlling the flow of the buffered digital signal includes the steps of allowing locally generated data to be coupled to the output before coupling the buffered signal to the output and waiting additional time after detecting the presence of valid data before coupling the buffered digital signal to the output, the additional time being the delay available from the count interval during which it was estimated that valid data began until the buffered digital signal has been buffered for at least N successive count intervals.
Claim 9
Dependent Claim
139 words
A signal detector for detecting the presence of valid data within an incoming signal and for controlling the flow of the incoming signal to an output according to whether valid data is detected, comprising: means for buffering the incoming signal for at least the duration of a buffering time and for producing a buffered signal; means for examining the incoming signal to determine whether it constitutes valid data within the buffering time and continuing to examine the incoming signal until it is determined that it constitutes valid data within the buffering time; means for producing an estimate, after it is determined that the incoming signal constitutes valid data within the buffering time, of when during the buffering time the data became valid; and means for controlling the flow of the buffered signal to the output according to the estimate.
Claim 10
Dependent Claim
139 words
A signal detector for detecting the presence of valid data within an incoming signal and for controlling the flow of the incoming signal to an output according to whether valid data is detected, comprising: means for buffering the incoming signal for at least the duration of a buffering time and for producing a buffered signal; means for examining the incoming signal to determine whether it constitutes valid data within the buffering time and continuing to examine the incoming signal until it is determined that it constitutes valid data within the buffering time; means for producing an estimate, after it is determined that the incoming signal constitutes valid data within the buffering time, of when during the buffering time the data became valid; and means for controlling the flow of the buffered signal to the output according to the estimate.
Claim 11
Dependent Claim
33 words
The signal detector of claim 7 including means for controlling the flow of locally generated signals to the output according to the estimate of when during the buffering time the data became valid.
Claim 12
Dependent Claim
166 words
A digital signal detector for detecting the presence of valid digital data within an incoming digital signal and for controlling the flow of the incoming digital signal to an output according to whether valid digital data is detected, comprising: means for producing transition counts that indicate the relative degree of phase lock between the incoming digital signal and a local clock for the bits during successive count intervals; means for storing an integral number, N, of the most recent transition counts; means for buffering successive bits of the incoming digital signal during N successive count intervals and for producing a buffered digital signal; means for comparing a sum of the N most recent transition counts to a threshold, for each successive transition count produced; means for producing an estimate of the count interval during which data became valid, if the sum is at least equal to the threshold; and means for controlling the flow of the buffered digital signal to the output according to the estimate.
Claim 13
Dependent Claim
166 words
A digital signal detector for detecting the presence of valid digital data within an incoming digital signal and for controlling the flow of the incoming digital signal to an output according to whether valid digital data is detected, comprising: means for producing transition counts that indicate the relative degree of phase lock between the incoming digital signal and a local clock for the bits during successive count intervals; means for storing an integral number, N, of the most recent transition counts; means for buffering successive bits of the incoming digital signal during N successive count intervals and for producing a buffered digital signal; means for comparing a sum of the N most recent transition counts to a threshold, for each successive transition count produced; means for producing an estimate of the count interval during which data became valid, if the sum is at least equal to the threshold; and means for controlling the flow of the buffered digital signal to the output according to the estimate.
Claim 14
Dependent Claim
93 words
A digital signal detector according to claim 9 in which the means for producing an estimate of the count interval during which data became valid comprises means for comparing the N most recent transition counts and means for estimating that if the transition counts have approximately equal magnitudes, then valid data began during the earliest of the N most recent count intervals, or that if the transition counts differ significantly, then valid data began during the count interval for which the transition count increased significantly from transition counts stored for earlier count intervals.
Claim 15
Dependent Claim
63 words
A digital signal detector according to claim 9 in which the means for controlling the flow of the buffered digital signal includes means for allowing locally generated data to be coupled to the output before detecting the presence of valid data and means for coupling the buffered digital signal to the output without significant additional delay after detecting the presence of valid data.
Claim 16
Dependent Claim
99 words
A digital signal detector according to claim 9 in which the means for controlling the flow of the buffered digital signal includes means for allowing locally generated data to be coupled to the output before coupling the buffered signal to the output and means for waiting additional time after detecting the presence of valid data before coupling the buffered digital signal to the output, the additional time being the delay available from the count interval during which it was estimated that valid data began until the buffered digital signal has been buffered for at least N successive count intervals.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-06-28 | 1991-12-28 | 1992-06-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-06-28 | 1995-12-28 | 1996-06-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-06-28 | 1999-12-28 | 2000-06-28 | $7700.00 | Window Closed / Lapsed |