Two mask technique for planarized trench oxide isolation of integrated devices

Claim 2

A process for creating patterns suitable for forming dielectrically filled trenches of arbitrary width between active regions in a semiconductor substrate, comprising the steps of: defining for the semiconductor substrate an outer boundary encompassing at least one active region; using a fixed dimension, generically identified as lambda, to define a first polygon trench region approximately lambda wide inward of the outer boundary and a second polygon trench region approximately lambda wide outward of the active region; defining polygon plateau regions not exceeding approximately lambda in width at locations correspondingly inward and outward of the polygon trench regions, wherever the boundaries of the inward and outward polygon trench regions are separated by approximately two lambda or greater; defining polygon trench regions not exceeding approximately lambda in width at locations correspondingly inward and outward of the polygon plateau regions, wherever the boundaries of the inward and outward polygon plateau regions are separated by approxmiately two lambda or greater; repeating in succession the preceding two steps until the remaining regions are all separated by less than two lambda; shrinking the boundaries of the polygon trench regions by a fixed amount approaching one-half lambda and deleting polygon trench regions which shrink to a zero dimension; expanding the boundaries of the modified polygon trench regions by a fixed amount approaching lambda and deleting polygon plateau regions which shrink to a zero dimension; shrinking the boundary of the previously modified polygon trench regions by a fixed amount approaching one-half lambda to define the pattern for a first fabrication mask; and defining the pattern for a second fabrication mask in substantial correspondence to the active regions.

Claim 3

A process for creating patterns suitable for forming dielectrically filled trenches of arbitrary width between active regions in a semiconductor substrate, comprising the steps of: defining for the semiconductor substrate an outer boundary encompassing at least one active region; using a fixed dimension, generically identified as lambda, to define a first polygon trench region approximately lambda wide inward of the outer boundary and a second polygon trench region approximately lambda wide outward of the active region; defining polygon plateau regions not exceeding approximately lambda in width at locations correspondingly inward and outward of the polygon trench regions, wherever the boundaries of the inward and outward polygon trench regions are separated by approximately two lambda or greater; defining polygon trench regions not exceeding approximately lambda in width at locations correspondingly inward and outward of the polygon plateau regions, wherever the boundaries of the inward and outward polygon plateau regions are separated by approximately two lambda or greater; repeating in succession the preceding two steps until the remaining regions are all separated by less than two lambda; shrinking the boundaries of the polygon trench regions by a fixed amount approaching one-half lambda and deleting polygon trench regions which shrink to a zero dimension; expanding the boundaries of the modified polygon trench regions by a fixed amount approaching lambda and deleting polygon plateau regions which shrink to a zero dimension; shrinking the boundary of the previously modified polygon trench regions by a fixed amount approaching one-half lambda to define the pattern for a first fabrication mask; defining the pattern for a second fabrication mask in substantial correspondence to the active regions; and wherein lambda is defined as a variable relating at the minimum value to the photolithographic precision of the etch masks and at the maximum value to the conformal deposition characteristics of the dielectric within the trenches and etched plateau regions.

Claim 4

A process for creating patterns suitable for forming dielectrically filled trenches of arbitrary width between active regions in a semiconductor substrate, comprising the steps of: defining for the semiconductor substrate an outer boundary encompassing at least one active region; using a fixed dimension, generically identified as lambda, to define a first polygon trench region approximately lambda wide inward of the outer boundary and a second polygon trench region approximately lambda wide outward of the active region; defining polygon plateau regions not exceeding approximately lambda in width at locations correspondingly inward and outward of the polygon trench regions, wherever the boundaries of the inward and outward polygon trench regions are separated by approximately two lambda or greater; defining polygon trench regions not exceeding approximately lambda in width at locations correspondingly inward and outward of the polygon plateau regions, wherever the boundaries of the inward and outward polygon plateau regions are separated by approximately two lambda or greater; repeating in succession the preceding two steps until the remaining regions are all separated by less than two lambda; shrinking the boundaries of the polygon trench regions by a fixed amount approaching one-half lambda and deleting polygon trench regions which shrink to a zero dimension; expanding the boundaries of the modified polygon trench regions by a fixed amount approaching lambda and deleting polygon plateau regions which shrink to a zero dimension; shrinking the boundary of the previously modified polygon trench regions by a fixed amount approaching one-half lambda to define the pattern for a first fabrication mask; defining the pattern for a second fabrication mask in substantial correspondence to the active regions; and wherein lambda is defined as a variable relating at the minimum value to the photolithographic precision of the etch masks and at the maximum value to the conformal deposition characteristics of the dielectric within the trenches and etched plateau regions.

Claim 5

The process recited in claim 2, wherein the sizes and locations of the trench and plateau regions in the first etch mask are defined by software which functionally replicate the steps of a common mask analysis language on a CALMA layout system, where lambda is selected to have a value "X" and the steps are: INPUTMASK(ACTIVE,2 3,0-63) INPUTMASK(BOUND,63,0-63) INVERSE:=BOUND MINUS ACTIVE INT1:=UNDERSIZE(X,INVERSE) MO:=INVERSE MINUS INT1 INT2:=UNDERSIZE(X,INT1) INT3:=UNDERSIZE(X,INT2) M1:=INT2 MINUS INT3 INT4:=UNDERSIZE(X,INT3) INT5:=UNDERSIZE(X,INT4) M2:=INT4 MINUS INT5 INT6:=UNDERSIZE(X,INT5) INT7:=UNDERSIZE(X,INT6) M3:=INT6 MINUS INT7 INTn:=UNDERSIZE(X,INTn-1) INTn+1:-UNDERSIZE(X,INTn) Mi:=INTn MINUS INTn+1 O0:=MO OR M1 O1:=O0 OR M2 O2:=O1 OR M3 O3:=O2 OR M4 Oi:=Oi-1 OR Mi+1 TEMPA:=UNDERSIZE (0.49X,Oi) TEMPA2:=OVERSIZE (0.98X,010) MASKA:=UNDERSIZE (0.49X,011) MASKA2:=ACTIVE OR MASKA OUTPUTMASK(MASKA2,3 0).