US4752930A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Watch dog timer
Assignee: Mitsubishi Electric Corp
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Filing: 1986-06-23
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Granted: 1988-06-21
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Expires: 2006-06-23
Abstract
Abstract A watch dog timer (20) is controlled to permit or inhibit operation of a free run counter (3). When a flip-flop (14) is reset by a reset signal, no clock signal is supplied to the free run counter (3), the operation of which is then inhibited. When a microcomputer (1) outputs an address signal (5) and a write signal (6), an address decoder (12) decodes the address signal to open an AND gate (13), thereby to set the flip-flop (14). When the flip-flop (14) is set, and AND gate (17) is opened to supply clock pulses to the free run counter (3), which in turn starts counting the clock pulses. When the microcomputer (1) operates abnormally and no clear signal is supplied to the free run counter (3) from a clear decision circuit (2), the free run counter (3) outputs a signal indicating abnormal operation of the microcomputer (1) upon counting a prescribed counter value.
Inventors
- 👤 Fumihide Kitamura
- 👤 Yuuichi Saitoh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 20:09
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/0703; G06F11/0751; G06F11/0754; G06F11/0757
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
173 words
A watch dog timer for detecting abnormal operation of a computer, said watch dog timer comprising: means for detecting operation of said computer and for generating a detector signal indicating whether computer operation is normal or abnormal; counter means for counting clock signals generated by the computer; means for clearing said counter means in response to the detector signal indicating a normal operation of said count value during abnormal operation of said computer and, in response to counting of a predetermined count value during abnormal operation of said computer, outputting a watch dog signal indicating an abnormal operation of said computer; control means for inhibiting counting of said clock signals by said counter means in response to an external control signal indicating that a watch dog function is not required; and clear signal output inhibiting means for clearing said counter means on the basis of data and address supplied from said computer in normal operation of said computer and inhibiting output of a clear signal in response to abnormal operation of said computer.
Claim 2
Dependent Claim
173 words
A watch dog timer for detecting abnormal operation of a computer, said watch dog timer comprising: means for detecting operation of said computer and for generating a detector signal indicating whether computer operation is normal or abnormal; counter means for counting clock signals generated by the computer; means for clearing said counter means in response to the detector signal indicating a normal operation of said count value during abnormal operation of said computer and, in response to counting of a predetermined count value during abnormal operation of said computer, outputting a watch dog signal indicating an abnormal operation of said computer; control means for inhibiting counting of said clock signals by said counter means in response to an external control signal indicating that a watch dog function is not required; and clear signal output inhibiting means for clearing said counter means on the basis of data and address supplied from said computer in normal operation of said computer and inhibiting output of a clear signal in response to abnormal operation of said computer.
Claim 3
Dependent Claim
23 words
A watch dog timer in accordance with claim 1, wherein said counter means and said control means are formed by semiconductor integrated circuits.
Claim 4
Dependent Claim
152 words
A watch dog timer for detecting abnormal operation of a computer, said watch dog timer comprising: means for detecting operation of said computer and for generating a detector signal indicating whether computer operation is normal or abnormal; counter means for counting clock signals generated by the computer; means for clearing said counter means in response to the detector signal indicating a normal operation of said computer and, in response to counting of a predetermined count value during abnormal operation of said computer, outputting a watch dog signal indicating an abnormal operation of said computer; and control means for inhibiting counting of said clock signals by said counter means in response to an external control signal indicating that a watch dog function is not required, said control means including clock signal output inhibiting means for inhibiting supply of said clock signals to said counter means when said computer outputs a predetermined address signal.
Claim 5
Dependent Claim
152 words
A watch dog timer for detecting abnormal operation of a computer, said watch dog timer comprising: means for detecting operation of said computer and for generating a detector signal indicating whether computer operation is normal or abnormal; counter means for counting clock signals generated by the computer; means for clearing said counter means in response to the detector signal indicating a normal operation of said computer and, in response to counting of a predetermined count value during abnormal operation of said computer, outputting a watch dog signal indicating an abnormal operation of said computer; and control means for inhibiting counting of said clock signals by said counter means in response to an external control signal indicating that a watch dog function is not required, said control means including clock signal output inhibiting means for inhibiting supply of said clock signals to said counter means when said computer outputs a predetermined address signal.
Claim 6
Dependent Claim
23 words
A watch dog timer in accordance with claim 3, wherein said counter means and said control means are formed by semiconductor integrated circuits.
Claim 7
Dependent Claim
61 words
A watch dog timer in accordance with claim 3, wherein said clock signal output inhibiting means includes: a decoder for outputting a decoded signal in response to output of said predetermined address signal from said computer, and gate means for inhibiting supply of said clock signals to said counter means in response to supply of said decoded signal from said decoder.
Claim 8
Dependent Claim
47 words
A watch dog timer in accordance with claim 5, wherein said gate means includes means supplied with a write or read control signal from said computer for inhibiting output of said clock signals in response to supply of said decoded signal in write or read control operation.
Claim 9
Dependent Claim
37 words
A watch dog timer in accordance with claim 5, wherein said computer includes program memory, said address decoder including means for outputting said decoded signal on the basis of an address signal read from said program memory.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-06-21 | 1991-12-21 | 1992-06-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-06-21 | 1995-12-21 | 1996-06-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-06-21 | 1999-12-21 | 2000-06-21 | $7700.00 | Window Closed / Lapsed |