US4586180A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Microprocessor fault-monitoring circuit
Assignee: Siemens AG
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Filing: 1983-02-25
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Granted: 1986-04-29
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Expires: 2003-02-25
Abstract
Abstract A circuit is disclosed for fault-monitoring a microprocessor. The circuit includes an oscillator having an output signal of the same frequency as a test signal output of the microprocessor. The circuit also includes a binary counter. The microprocessor test output is coupled to the reset input of the counter and the oscillator is coupled to the counting input of the counter. The counter counts when the test signal does not correspond in frequency to the oscillator signal. A lower order output signal of the counter is used as a reset for the microprocessor and a higher order output of the counter is used to generate a fault indicating signal if the microprocessor has not resumed correct operation and to inhibit the microprocessor. The oscillator is coupled to the counting input of the counter through a logic circuit. The two outputs of the counter are coupled to another logic circuit which supplies the reset and inhibit signals to the microprocessor. A fault indicator is also coupled to the higher order output of the counter. The invention is advantageous in that only a small amount of circuitry is required to provide the monitoring functions disclosed herein.
Inventors
- 👤 Horst-Gunther Anders
- 👤 Rudolf Diepold-Scharnitzky
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 14:01
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/0703; G06F11/0751; G06F11/0754; G06F11/0757; G06F11/14; G06F11/1402; G06F11/1415
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
301 words
A circuit arrangement for monitoring the program operation of a computer means comprising binary counter means having a counting input, a reset input and a plurality of outputs, the reset input being coupled to an output of the computer means, and further including oscillator means, said plurality of outputs of said counter means comprising a lower order output and a higher order output, said lower order and higher order outputs being coupled to respective first and second inputs of first logic circuit means, an output of said logic circuit means being coupled to a reset input of said computer means, said output of said computer means comprising a test signal, the frequency of said test signal being substantially the same as the frequency of the output of said oscillator means when said computer means is functioning properly, and further comprising second logic circuit means having two inputs and an output, the output of said oscillator means being coupled to a first input of said second logic circuit means, the output of said second logic circuit means being coupled to said counting input of said counter means, said higher order output being further coupled to the second input of said second logic circuit means, so that if said lower order output attains a logic one condition, said computer means will be reset and if said higher order output attains a logic one condition, said computer means will be reset and said counter means will be disabled, thereby retaining said logic one condition at said higher order output, thus placing said computer means in a locked condition so that no further operation of said computer means can occur, and further comprising means for generating a fault indication signal coupled to said higher order output of said counter means for indicating a locked condition.
Claim 2
Dependent Claim
301 words
A circuit arrangement for monitoring the program operation of a computer means comprising binary counter means having a counting input, a reset input and a plurality of outputs, the reset input being coupled to an output of the computer means, and further including oscillator means, said plurality of outputs of said counter means comprising a lower order output and a higher order output, said lower order and higher order outputs being coupled to respective first and second inputs of first logic circuit means, an output of said logic circuit means being coupled to a reset input of said computer means, said output of said computer means comprising a test signal, the frequency of said test signal being substantially the same as the frequency of the output of said oscillator means when said computer means is functioning properly, and further comprising second logic circuit means having two inputs and an output, the output of said oscillator means being coupled to a first input of said second logic circuit means, the output of said second logic circuit means being coupled to said counting input of said counter means, said higher order output being further coupled to the second input of said second logic circuit means, so that if said lower order output attains a logic one condition, said computer means will be reset and if said higher order output attains a logic one condition, said computer means will be reset and said counter means will be disabled, thereby retaining said logic one condition at said higher order output, thus placing said computer means in a locked condition so that no further operation of said computer means can occur, and further comprising means for generating a fault indication signal coupled to said higher order output of said counter means for indicating a locked condition.
Claim 3
Dependent Claim
17 words
The circuit arrangement recited in claim 1 wherein said first and second logic circuits comprise OR gates.
Claim 4
Dependent Claim
22 words
The circuit arrangement recited in claim 1 wherein said lower order and higher order outputs are non-adjacent outputs of said counter means.
Claim 5
Dependent Claim
37 words
The circuit arrangement recited in claim 1 wherein said counter means is a four bit binary counter and said lower order output is the second bit output and said higher order output is said fourth bit output.
Claim 6
Dependent Claim
43 words
The circuit arrangement recited in claim 1 further comprising switch means coupled to said higher order output of said counter means for temporarily disabling said output so that said computer means can be unlocked after said computer means goes into a locked state.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-04-28 | 1989-10-28 | 1990-04-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-04-28 | 1993-10-28 | 1994-04-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-04-28 | 1997-10-28 | 1998-04-29 | $7700.00 | Window Closed / Lapsed |