System failure monitor title

Claim 3

Apparatus for monitoring operations of a programmable machine means comprising, in combination; first means for periodically interrupting normal program operation of the machine means and for commencing a multistate diagnostic test routine including a reset instruction; second means connected to said first means for commencing counting on a recycling basis the number of states completed in said test routine in response to a signal from said first means; third means for providing an output upon occurrence of said reset instruction; and first logic means connected to said third means and said second means for receiving signals therefrom for providing a machine failure indication when said reset instruction occurs at a time other than a predetermined count by said second means.

Claim 4

Apparatus for monitoring operations of a programmable machine means comprising, in combination; first means for periodically interrupting normal program operation of the machine means and for commencing a multistate diagnostic test routine including a reset instruction; second means connected to said first means for commencing counting on a recycling basis the number of states completed in said test routine in response to a signal from said first means; third means for providing an output upon occurrence of said reset instruction; and first logic means connected to said third means and said second means for receiving signals therefrom for providing a machine failure indication when said reset instruction occurs at a time other than a predetermined count by said second means.

Claim 5

Apparatus as claimed in claim 2 comprising, in addition: fourth means for providing an output signal in response to the passage of a predetermined time after commencement of said diagnostic test routine; and further logic means connected to said first logic means for providing a machine failure indication when said reset instruction does not occur within said predetermined time.

Claim 6

Monitoring apparatus comprising, in combination: computer apparatus means including priority program interrupt means, interrupting normal low priority program operations in the computer apparatus; resettable first means for periodically providing a signal to said priority interrupt means whereby said computer apparatus commences a multiple state diagnostic test routine containing at least one reset instruction; second means for providing an output signal a predetermined time after commencement of said multiple state diagnostic test routine; reset third means for providing an output signal upon occurrence of said reset instruction in said diagnostic test routine; and failure indicating fourth means connected to said third means and to said second meAns for providing a failure output if said second means provides an output signal prior to an output signal being obtained from said third means.

Claim 7

Monitoring apparatus comprising, in combination: computer apparatus means including priority program interrupt means, interrupting normal low priority program operations in the computer apparatus; resettable first means for periodically providing a signal to said priority interrupt means whereby said computer apparatus commences a multiple state diagnostic test routine containing at least one reset instruction; second means for providing an output signal a predetermined time after commencement of said multiple state diagnostic test routine; reset third means for providing an output signal upon occurrence of said reset instruction in said diagnostic test routine; and failure indicating fourth means connected to said third means and to said second meAns for providing a failure output if said second means provides an output signal prior to an output signal being obtained from said third means.

Claim 8

Apparatus as claimed in claim 4 including means for receiving said output signal from said third means and thereupon resetting said first means to an initial condition.

Claim 9

Apparatus as claimed in claim 5 comprising in addition: state count fifth means for counting the number of states completed in said diagnostic test routine and for providing an output indicative of the completion of a predetermined number of states; and further means connected to said third means and said fifth means for providing a failure indication when said output signal of said third means occurs at a time other than coincident with the output signal from said fifth means.

Claim 10

In the operation of computing apparatus, a new method of detecting failure of a program operation portion of said computing apparatus, said computing apparatus being interconnected to include: priority interrupt means for interrupting normal program operations; logic means; timing means; and failure indicating means; said new method comprising; initiating a multistep test routine periodically in accordance with an output from said timing means; providing a reset instruction in said test routine for resetting said timing means upon the occurrence thereof; providing an output signal indicative of computing apparatus failure when said reset instruction output is not obtained within a predetermined time after initiation of said multistep test routine; and resuming normal program operations upon completion of the test routine when no failure output signal is provided.

Claim 11

In the operation of computing apparatus, a new method of detecting failure of a program operation portion of said computing apparatus, said computing apparatus being interconnected to include: priority interrupt means for interrupting normal program operations; logic means; timing means; and failure indicating means; said new method comprising; initiating a multistep test routine periodically in accordance with an output from said timing means; providing a reset instruction in said test routine for resetting said timing means upon the occurrence thereof; providing an output signal indicative of computing apparatus failure when said reset instruction output is not obtained within a predetermined time after initiation of said multistep test routine; and resuming normal program operations upon completion of the test routine when no failure output signal is provided.

Claim 12

The method of claim 7 wherein a state counting means is additionally interconnected in said computing apparatus and comprising the additional steps of: counting the steps completed in the test routine; and providing an output indicative of computer system failure when the reset instruction output occurs noncoincidentally with a predetermined number of completed steps in the test routine.