Random access memory employing complementary transistor switch (CTS) memory cells

Claim 2

A monolithic random access memory for storing binary data, said memory comprising: an array of memory cells having m columns and n rows, where m and n are positive integers, and said memory array including m×n memory cells, where each of said cells has the capacity to store one binary bit and each of said n rows of memory cells has the capacity to store m binary bits; m pairs of bit lines, each pair of said m pairs of bit lines including a first bit line BL and a second line BR; n pairs of word lines, each pair of said n pairs of word lines including an upper word line and a lower (drain) word line; each of said memory cells of said m×n array of memory cells being connected to the first bit line BL and the second bit line BR of a predetermined one of said m pairs of bit lines; each of said memory cells of said m×n array of memory cells being also connected to the upper word line and the lower (drain) word line of a predetermined one of said n pairs of word lines; m bit select circuits, each of said m bit select circuits having an input terminal, and a pair of output terminals connected to a discrete one of said m pairs of bit lines; a switchable bit up level clamp circuit having an output terminal connected to each of said m bit select circuits; bit address decoder circuit means coupled to said m bit select circuits for selecting at least one of said m bit select circuits; and word line decoder circuit means coupled to said n pairs of word lines for selecting one of said n pairs of word lines, whereby the operation of said bit address decoder circuit means in conjunction with the operation of said word line decoder circuit means selects at least a predetermined one of said m×n array of memory cells, said monolithic random access memory being further characterized in that each of said m bit select circuits includes boot-strap circuit means, for increasing the read/write speed of the memory said boot-strap circuit means including first and second transistors, said first and second transistors each having an emitter, base, and collector, said collector of said first transistor connected to the input terminal of a discrete one of said m bit select circuits, a first resistor connected between the emitter of said first transistor and the first bit line BL of an associated one of said m pairs of bit lines, said collector of said second transistor connected to the input terminal of said discrete one of said m bit select circuits, and a second resistor connected between the emitter of said second transistor and the second bit line BR of said associated one of said m pairs of bit lines , a third transistor having a collector, base, and emitter, said third transistor emitter being connected to the first bit line BL of said associated one of said m pairs of bit lines and said third transistor base being connected to the base of said first transistor, a fourth transistor having a collector, base, and emitter, said fourth transistor emitter being connected to the second bit line BR of said associated one of said m pairs of bit lines and said fourth transistor base being connected to the base of said second transistor.

Claim 3

A monolithic random access memory for storing binary data, as recited in claim 1, wherein each of said boot-strap circuit means further includes first and second parallel circuits, said first parallel circuit connected between said input terminal of said discrete one of said m bit select circuits and the first bit line BL of said associated one of said m pairs of bit lines, said second parallel circuit connected between said input terminal of said discrete one of said m bit select circuits and the second bit line BR of said associated one of said m pairs of bit lines, and each of said first and second parallel circuits including a resistor and a Schottky diode connected in parallel.

Claim 4

A monolithic random access memory for storing binary data, said memory comprising: an array of memory cells having m columns and n rows, where m and n are positive integers, and said memory array including m×n memory cells, where each of said cells has the capacity to store one binary bit and each of said n rows of memory cells has the capacity to store m binary bits; m pairs of bit lines, each pair of said m pairs of bit lines including a first bit line BL and a second bit line BR; n pairs of word lines each pair of said n pairs of word lines including an upper word line and a lower (drain) word line; each of said memory cells of said m×n array of memory cells being connected to the first bit line BL and the second bit line BR of a predetermined one of said m pairs of bit lines; each of said memory cells of said m×n array of memory cells being also connected to the upper word line and the lower (drain) word line of a predetermined one of said n pairs of word lines; m bit select circuits, each of said m bit select circuits being connected to a discrete one of said m pairs of bit lines; a switchable bit up level clamp circuit having an output terminal connected to each of said m bit select circuits; bit address decoder circuit means coupled to said m bit select circuits for selecting at least one of said m bit select circuits; word line decoder circuit means coupled to said n pairs of word lines for selecting one of said n pairs of word lines; and, said monolithic random access memory being further characterized in that each of said m bit select circuits includes, first, second, third, fourth, fifth and sixth transistors, said first, second, third and fourth transistors each having an emitter, base and collector, said fifth and sixth transistors each having first and second emitters, a base and a collector, said collector of said first transistor connected to a first source of potential, said collector of said second transistor connected to said first source of potential, first connection means connecting in common said base of said first transistor, said base of said third transistor, said collector of said fifth transistor and said base of said fifth transistor, second connection means connecting in common said base of said second transistor, said base of said fourth transistor, said collector of said sixth transistor and said base of said sixth transistor, third connection means connecting in common said collector of said third transistor, said collector of said fourth transistor and said bit address decoder circuit means, a first resistor connected between said base of said first transistor and said first source of potential; a second resistor connected between said base of said second transistor and said first source of potential, a third resistor connected between said emitter of said first transistor and said emitter of said third transistor, a fourth resistor connected between said emitter of said second transistor and said emitter of said fourth transistor, a fifth resistor connected between said emitter of said first transistor and said collector of said third transistor, a sixth resistor connected between said emitter of said second transistor and said collector of said fourth transistor, a first Schottky diode connected in parallel with said fifth resistor, a second Schottky diode connected in parallel with said sixth resistor, the first bit line (BL) of an associated one of said m pairs of bit lines being connected to said emitter of said first transistor, the second bit line (BR) of said associated one of said m pairs of bit lines being connected to said emitter of said second transistor, a third Schottky diode connected between the first bit line of an associated one of said m pairs of bit lines and said first emitter of said fifth transistor, a fourth Schottky diode connected between the second bit line of said associated one of said m pairs of bit lines and said first emitter of said sixth transistor, a common connection between said second emitters of said fifth and sixth transistors and said switchable bit up level clamp circuit output terminal, and said first emitters of said fifth and sixth transistors being connected to a write control circuit.

Claim 5

A monolithic random access memory for storing binary data, said memory comprising: an array of memory cells having m columns and n rows, where m and n are positive integers, and said memory array including m×n memory cells, where each of said cells has the capacity to store one binary bit and each of said n rows of memory cells has the capacity to store m binary bits; m pairs of bit lines, each pair of said m pairs of bit lines including a first bit line BL and a second bit line BR; n pairs of word lines each pair of said n pairs of word lines including an upper word line and a lower (drain) word line; each of said memory cells of said m×n array of memory cells being connected to the first bit line BL and the second bit line BR of a predetermined one of said m pairs of bit lines; each of said memory cells of said m×n array of memory cells being also connected to the upper word line and the lower (drain) word line of a predetermined one of said n pairs of word lines; m bit select circuits, each of said m bit select circuits being connected to a discrete one of said m pairs of bit lines; a switchable bit up level clamp circuit having an output terminal connected to each of said m bit select circuits; bit address decoder circuit means coupled to said m bit select circuits for selecting at least one of said m bit select circuits; word line decoder circuit means coupled to said n pairs of word lines for selecting one of said n pairs of word lines; and, said monolithic random access memory being further characterized in that each of said m bit select circuits includes, first, second, third, fourth, fifth and sixth transistors, said first, second, third and fourth transistors each having an emitter, base and collector, said fifth and sixth transistors each having first and second emitters, a base and a collector, said collector of said first transistor connected to a first source of potential, said collector of said second transistor connected to said first source of potential, first connection means connecting in common said base of said first transistor, said base of said third transistor, said collector of said fifth transistor and said base of said fifth transistor, second connection means connecting in common said base of said second transistor, said base of said fourth transistor, said collector of said sixth transistor and said base of said sixth transistor, third connection means connecting in common said collector of said third transistor, said collector of said fourth transistor and said bit address decoder circuit means, a first resistor connected between said base of said first transistor and said first source of potential; a second resistor connected between said base of said second transistor and said first source of potential, a third resistor connected between said emitter of said first transistor and said emitter of said third transistor, a fourth resistor connected between said emitter of said second transistor and said emitter of said fourth transistor, a fifth resistor connected between said emitter of said first transistor and said collector of said third transistor, a sixth resistor connected between said emitter of said second transistor and said collector of said fourth transistor, a first Schottky diode connected in parallel with said fifth resistor, a second Schottky diode connected in parallel with said sixth resistor, the first bit line (BL) of an associated one of said m pairs of bit lines being connected to said emitter of said first transistor, the second bit line (BR) of said associated one of said m pairs of bit lines being connected to said emitter of said second transistor, a third Schottky diode connected between the first bit line of an associated one of said m pairs of bit lines and said first emitter of said fifth transistor, a fourth Schottky diode connected between the second bit line of said associated one of said m pairs of bit lines and said first emitter of said sixth transistor, a common connection between said second emitters of said fifth and sixth transistors and said switchable bit up level clamp circuit output terminal, and said first emitters of said fifth and sixth transistors being connected to a write control circuit.

Claim 6

A monolithic random access memory for storing binary data, as recited in claim 3, wherein each of said memory cells is a CTS (complementary transistor switch) memory cell.

Claim 7

A monolithic random access memory for storing binary data as recited in claim 3, wherein each of said memory cells is an "unclamped" CTS (complementary transistor switch) memory cell.

Claim 8

A monolithic random access memory for storing binary data, as recited in claim 3, wherein each of said memory cells comprises: seventh, eighth, ninth and tenth transistors, each of said seventh through tenth transistors having an emitter, base and collector, said ninth and tenth transistors being of opposite conductivity type to that of said first through eighth transistors; a first common connection of said emitters of ninth and tenth transistors and the upper word line of a corresponding pair of said n pairs of word lines; a second common connection of said emitters of said seventh and eighth transistors and the lower (drain) word line of said corresponding pair of said n pairs of word lines; a third common connection of said collector of said ninth transistor, said base of said seventh transistor, said collector of said eighth transistor and said base of said tenth transistor; a fourth common connection of said collector of said tenth transistor, said base of said eighth transistor, said collector of said seventh transistor and said base of said ninth transistor; a fifth Schottky diode connected between said base of said ninth transistor and the first bit line BL of a respective pair of said m pairs of bit lines; and, a sixth Schottky diode connected between said base of said tenth transistor and the second bit line BR of said respective pair of said m pairs of bit lines.

Claim 9

A monolithic random access memory for storing binary data, as recited in claim 3, wherein said switchable bit up level clamp includes a read/write control input, said switchable bit up level clamp limiting the up potential of the bit line pair selected in response to said read/write control input calling for a write operation.

Claim 10

A monolithic random access memory for storing binary data, as recited in claim 7, wherein said switchable bit up level clamp circuit comprises current switch circuit means and said read/write control input is the switchable control thereof.

Claim 11

A monolithic random access memory for storing binary data, as recited in claim 8, wherein said switchable bit up level clamp circuit comprises: seventh, eighth, ninth, tenth and eleventh transistors, each of said seventh, eighth, ninth, tenth and eleventh transistors having an emitter, base and collector, said emitters of said seventh and eighth transistors being connected in common, said read/write control input of said switchable bit up level clamp circuit being connected to said base of said seventh transistor, said base of said eighth transistor being connected to a first reference source of potential, said collector of said eighth transistor being connected to said base of said ninth transistor, said collector of said ninth transistor being connected to said base of said tenth transistor, said collector of said tenth transistor being connected to said first source of potential, said collector of said eleventh transistor being connected to said emitter of said tenth transistor, said base of said eleventh transistor being connected to said emitter of said ninth transistor, and said collector of said seventh transistor being connected to said first source of potential; a seventh resistor, said seventh resistor connecting said collector of said eighth transistor to said first source of potential; an eighth resistor, said eighth resistor connecting the common connection of said emitters of said seventh and eighth transistors to a second source of potential; a ninth resistor, said ninth resistor connecting said collector of said ninth transistor to said first source of potential; a tenth resistor, said tenth resistor connecting said emitter of said ninth transistor to said second source of potential; an eleventh resistor, a fifth diode and a sixth diode, said eleventh resistor, said fifth diode and said sixth diode being serially connected between said collector of said ninth transistor and said second source of potential; a seventh diode, being connected between said emitter of said eleventh transistor and said second source of potential; and, said switchable bit up level clamp circuit output terminal being connected to said emitter of said tenth transistor in each one of said m bit select circuits.

Claim 12

In a monolithic random access memory for storing binary data, as recited in claim 9, wherein said fifth, sixth and seventh diodes are respectively "diode-connected" transistors.