Patent US4751406A successfully refreshed from Google Patents.
US4751406A
Expired / Lapsed
US
⏱️ 0.0 years remaining
ECL circuit with output transistor auxiliary biasing circuit
Assignee: Advanced Micro Devices Inc
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Filing: 1985-05-03
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Granted: 1988-06-14
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Expires: 2005-05-03
Abstract
Abstract An ECL circuit comprising an output transistor having a base, a resistor coupled to the base, a first circuit responsive to a deselect signal OE for drawing a first current through the resistor and a second circuit responsive to the deselect signal OE for drawing a second current through the resistor, said first and said second currents combining in said resistor for providing a predetermined turn-off bias potential on said base of said output transistor. The predetermined turn-off bias potential reduces the emitter current of the output transistor such that the noise immunity of a data bus is preserved when a plurality of output transistors are coupled in parallel to the data bus.
Inventors
- 👤 Stanley Wilson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 22:10
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/082; H03K19/086; H03K19/0866; H03K17/00; H03K17/51; H03K17/56; H03K17/60; H03K17/603; H03K17/62; H03K17/6257; H03K17/6264; H03K19/003; H03K19/00346; H03K19/00353
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
199 words
An ECL circuit for providing noise immunity on a data bus when a plurality of such circuits are coupled in parallel to said bus comprising: an output transistor coupled to said data bus and having a base; a first pair of transistor means responsive to complementary data signals and coupled to said output transistor for providing corresponding data signals on said bus; a second pair of transistor means responsive to complementary output enable control signals and coupled to said output transistor for providing a first level of turn-off bias potential on said base of said output transistor; a first current source coupled to said first and said second pair of transistor means for controlling the magnitude of said first level of turn-off bias potential; a third pair of transistor means responsive to said complementary output enable control signals and coupled to said output transistor for providing an auxiliary turn-off bias potential on said base of said output transistor; and a second current source coupled to said third pair of transistor means for controlling the magnitude of said auxiliary turn-off bias potential, said magnitude of said auxiliary bias potential being a fraction of said first level of turn-off bias potential.
Claim 2
Dependent Claim
199 words
An ECL circuit for providing noise immunity on a data bus when a plurality of such circuits are coupled in parallel to said bus comprising: an output transistor coupled to said data bus and having a base; a first pair of transistor means responsive to complementary data signals and coupled to said output transistor for providing corresponding data signals on said bus; a second pair of transistor means responsive to complementary output enable control signals and coupled to said output transistor for providing a first level of turn-off bias potential on said base of said output transistor; a first current source coupled to said first and said second pair of transistor means for controlling the magnitude of said first level of turn-off bias potential; a third pair of transistor means responsive to said complementary output enable control signals and coupled to said output transistor for providing an auxiliary turn-off bias potential on said base of said output transistor; and a second current source coupled to said third pair of transistor means for controlling the magnitude of said auxiliary turn-off bias potential, said magnitude of said auxiliary bias potential being a fraction of said first level of turn-off bias potential.
Claim 3
Dependent Claim
45 words
An ECL circuit according to claim 1 wherein said auxiliary turn-off bias potential transistor providing means comprises means for providing a predetermined amount of auxiliary turn-off bias potential to said first level of turn-off bias potential provided by said second pair of transistor circuit means.
Claim 4
Dependent Claim
65 words
An ECL circuit according to claim 2 comprising a first, a second and a third resistor and wherein the magnitude of said first level of turn-off bias potential corresponds to the ratio of the magnitudes of said first and said second resistors and the magnitude of said auxiliary turn-off bias potential corresponds to the ratio of the magnitudes of said first and said third resistors.
Claim 5
Dependent Claim
29 words
An ECL circuit according to claim 3 wherein said magnitudes of said first, said second and said third resistors comprise approximately 309 ohms, 193 ohms and 1931 ohms, respectively.
Claim 6
Dependent Claim
45 words
An ECL circuit according to claim 3 wherein said magnitude of said first level of turn-off potential comprises approximately -0.8 volts and said magnitude of said auxiliary turn-off bias potential comprises approximately -0.08 volts for providing a total turn-off bias potential of approximately -0.88 volts.
Claim 7
Dependent Claim
268 words
An ECL circuit for providing noise immunity on a data bus when a plurality of such circuits are coupled in parallel to said bus comprising: an output transistor coupled to said data bus and having a base; a first pair of transistor means responsive to complementary data signals and coupled to said output transistor for providing corresponding data signals on said bus; a second pair of transistor means responsive to complementary output enable control signals and coupled to said output transistor for providing a first level of turn-off bias potential on said base of said output transistor; a first current source coupled to said first and said second pair of transistor means for controlling the magnitude of said first level of turn-off bias potential; a third pair of transistor means responsive to said complementary output enable control signals and coupled to said output transistor for providing a predetermined amount of auxiliary turn-off bias potential on said base of said output transistor; a second current source coupled to said third pair of transistor means for controlling the magnitude of said auxiliary turn-off bias potential, said magnitude of said auxiliary bias potential being a fraction of said first level of turn-off bias potential; and a first, a second and a third resistor comprising 309 ohms, 193 ohms and 1164 ohms, respectively and wherein the magnitude of said first level of turn-off bias potential corresponds to the ratio of the magnitudes of said first and said second resistors and the magnitude of said auxiliary turn-off bias potential corresponds to the ratio of the magnitudes of said first and said third resistors.
Claim 8
Dependent Claim
268 words
An ECL circuit for providing noise immunity on a data bus when a plurality of such circuits are coupled in parallel to said bus comprising: an output transistor coupled to said data bus and having a base; a first pair of transistor means responsive to complementary data signals and coupled to said output transistor for providing corresponding data signals on said bus; a second pair of transistor means responsive to complementary output enable control signals and coupled to said output transistor for providing a first level of turn-off bias potential on said base of said output transistor; a first current source coupled to said first and said second pair of transistor means for controlling the magnitude of said first level of turn-off bias potential; a third pair of transistor means responsive to said complementary output enable control signals and coupled to said output transistor for providing a predetermined amount of auxiliary turn-off bias potential on said base of said output transistor; a second current source coupled to said third pair of transistor means for controlling the magnitude of said auxiliary turn-off bias potential, said magnitude of said auxiliary bias potential being a fraction of said first level of turn-off bias potential; and a first, a second and a third resistor comprising 309 ohms, 193 ohms and 1164 ohms, respectively and wherein the magnitude of said first level of turn-off bias potential corresponds to the ratio of the magnitudes of said first and said second resistors and the magnitude of said auxiliary turn-off bias potential corresponds to the ratio of the magnitudes of said first and said third resistors.
Claim 9
Dependent Claim
273 words
An ECL circuit for providing noise immunity on a data bus when a plurality of such circuits are coupled in parallel to said bus comprising: an output transistor coupled to said data bus and having a base; a first pair of transistor means responsive to complementary data signals and coupled to said output transistor for providing corresponding data signals on said bus; a second pair of transistor means responsive to complementary output enable control signals and coupled to said output transistor for providing a first level of turn-off bias potential on said base of said output transistor having a magnitude of approximately -0.8 volts; a first current source coupled to said first and said second pair of transistor means for controlling the magnitude of said first level of turn-off bias potential; a third pair of transistor means responsive to said complementary output enable control signals and coupled to said output transistor for providing a predetermined amount of auxiliary turn-off bias potential on said base of said output transistor having a magnitude of approximately -0.08 volts; a second current source coupled to said third pair of transistor means for controlling the magnitude of said auxiliary turn-off bias potential, said magnitude of said auxiliary bias potential being a fraction of said first level of turn-off bias potential; and a first, a second and a third resistor and wherein the magnitude of said first level of turn-off bias potential corresponds to the ratio of the magnitudes of said first and said second resistors and the magnitude of said auxiliary turn-off bias potential corresponds to the ratio of the magnitudes of said first and said third resistors.
Claim 10
Dependent Claim
273 words
An ECL circuit for providing noise immunity on a data bus when a plurality of such circuits are coupled in parallel to said bus comprising: an output transistor coupled to said data bus and having a base; a first pair of transistor means responsive to complementary data signals and coupled to said output transistor for providing corresponding data signals on said bus; a second pair of transistor means responsive to complementary output enable control signals and coupled to said output transistor for providing a first level of turn-off bias potential on said base of said output transistor having a magnitude of approximately -0.8 volts; a first current source coupled to said first and said second pair of transistor means for controlling the magnitude of said first level of turn-off bias potential; a third pair of transistor means responsive to said complementary output enable control signals and coupled to said output transistor for providing a predetermined amount of auxiliary turn-off bias potential on said base of said output transistor having a magnitude of approximately -0.08 volts; a second current source coupled to said third pair of transistor means for controlling the magnitude of said auxiliary turn-off bias potential, said magnitude of said auxiliary bias potential being a fraction of said first level of turn-off bias potential; and a first, a second and a third resistor and wherein the magnitude of said first level of turn-off bias potential corresponds to the ratio of the magnitudes of said first and said second resistors and the magnitude of said auxiliary turn-off bias potential corresponds to the ratio of the magnitudes of said first and said third resistors.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-06-14 | 1991-12-14 | 1992-06-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-06-14 | 1995-12-14 | 1996-06-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-06-14 | 1999-12-14 | 2000-06-14 | $7700.00 | Window Closed / Lapsed |