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Patent US4750971A successfully refreshed from Google Patents.
US4750971A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of manufacturing a semiconductor device
Assignee: US Philips Corp
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Filing: 1987-01-27
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Granted: 1988-06-14
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Expires: 2007-01-27
Abstract
Abstract An improved method of manufacturing a semiconductor device having a narrow groove or slot is provided. There are formed on a substrate a heavily n-doped first silicon layer, and oxidation-preventing layer such as silicon nitride, and a weakly doped or undoped second silicon layer. By means of a single masking step, a part of the second silicon layer is removed to exposed portions of the oxidation preventing layer, and the remaining part is partially oxidized. A particle bombardment of the exposed portions of the oxidation-preventing layer is carried out with the oxidized part of the second silicon layer being a mask. Subsequently, the oxide on the second silicon layer is removed leaving non-exposed portions of the oxidation-preventing layer, and then the exposed portions of the oxidation-preventing layer on the first silicon layer are completely etched away. By thermal oxidation, a thin oxide layer is formed on the second silicon layer and an about ten times thicker oxide layer is formed on the first silicon layer. After the non-exposed portion of the oxidation-preventing layer has been etched away, the thin oxide layer on the second silicon layer is etched away entirely and the thicker oxide on the first silicon layer is etched away only superficially. After this, a groove is etched into the first silicon layer at the removed non-exposed portions of the oxidation-preventing layer while simultaneously removing the remaining parts of the second silicon layer.
Inventors
- 👤 Henricus G. R. Maas
- 👤 Johannes A. Appels
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 08:30
CPC Classifications
H; H10; H10D; H10D44/00; H10D44/01; H10D44/041; H10P; H10P50/00; H10P50/69; H10P50/691; H10P76/00; H10P76/40; H10P95/00; Y; Y10; Y10S; Y10S438/00; Y10S438/911; Y10S438/981
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
360 words
A method of manufacturing a semiconductor device comprising the steps of forming an oxidation-preventing layer on a first layer of silicon, forming a second layer of silicon on said oxidation-preventing layer, removing at least one portion of said second silicon layer from said oxidation-preventing layer, oxidizing all exposed surfaces of the remaining parts of said second silicon layer, carrying out a particle bombardment of exposed portions of said oxidation-preventing layer with said oxidized remaining parts of said second silicon layer serving as masks, said particle bombardment providing the exposed portions of the oxidation-preventing layer with a higher etching rate than masked portions of said oxidation-preventing layer, removing the oxidized surface parts of said second silicon layer by etching to expose non-bombarded portions of said oxidation-preventing layer, completely etching away said exposed bombarded portions of said oxidation-preventing layer on said first silicon layer, and only superfically etching away said exposed non-bombarded portions of said oxidation-preventing layer, thermally oxidizing exposed portions of said first silicon layer and said remaining exposed parts of said second silicon layer to form a thick oxide layer on said first silicon layer and a thinner oxide layer on said remaining exposed parts of said second silicon layer such that the thinner oxide layer does not entirely cover said exposed non-bombarded portions of said oxidation-preventing layer, removing said exposed non-bombarded portions of said oxidation-preventing layer by etching, entirely removing said thinner oxide layer on said remaining parts of said second silicon layer by mask-free etching, wherein upper parts of said thick oxide layer are removed while lower parts of said thick oxide layer remain on said first silicon layer, etching at least one groove into said first silicon layer at said removed non-bombarded portions of said oxidation-preventing layer, said groove separating a first part of said first silicon layer from a second part of said first silicon layer, said first part of said first silicon layer being strongly n-type conducting, and said first part having a higher doping concentration than at least said remaining part of said second silicon layer, and during said etching of at least one groove, removing said remaining parts of said second silicon layer
Claim 2
Independent Claim
360 words
A method of manufacturing a semiconductor device comprising the steps of forming an oxidation-preventing layer on a first layer of silicon, forming a second layer of silicon on said oxidation-preventing layer, removing at least one portion of said second silicon layer from said oxidation-preventing layer, oxidizing all exposed surfaces of the remaining parts of said second silicon layer, carrying out a particle bombardment of exposed portions of said oxidation-preventing layer with said oxidized remaining parts of said second silicon layer serving as masks, said particle bombardment providing the exposed portions of the oxidation-preventing layer with a higher etching rate than masked portions of said oxidation-preventing layer, removing the oxidized surface parts of said second silicon layer by etching to expose non-bombarded portions of said oxidation-preventing layer, completely etching away said exposed bombarded portions of said oxidation-preventing layer on said first silicon layer, and only superfically etching away said exposed non-bombarded portions of said oxidation-preventing layer, thermally oxidizing exposed portions of said first silicon layer and said remaining exposed parts of said second silicon layer to form a thick oxide layer on said first silicon layer and a thinner oxide layer on said remaining exposed parts of said second silicon layer such that the thinner oxide layer does not entirely cover said exposed non-bombarded portions of said oxidation-preventing layer, removing said exposed non-bombarded portions of said oxidation-preventing layer by etching, entirely removing said thinner oxide layer on said remaining parts of said second silicon layer by mask-free etching, wherein upper parts of said thick oxide layer are removed while lower parts of said thick oxide layer remain on said first silicon layer, etching at least one groove into said first silicon layer at said removed non-bombarded portions of said oxidation-preventing layer, said groove separating a first part of said first silicon layer from a second part of said first silicon layer, said first part of said first silicon layer being strongly n-type conducting, and said first part having a higher doping concentration than at least said remaining part of said second silicon layer, and during said etching of at least one groove, removing said remaining parts of said second silicon layer
Claim 3
Dependent Claim
51 words
A method according to claim 1, wherein said thinner oxide layer on said remaining part of said second silicon layer is removed in a first plasma after removing said exposed non-bombardment portions of said oxidation-preventing layer, and wherein said groove is etched by a second plasma in a continuous etching process.
Claim 4
Dependent Claim
26 words
A method according to claim 2, wherein said first plasma is a carbon tetrachloride (CCl 4 ) plasma, and said second plasma is a chlorine plasma.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-06-14 | 1991-12-14 | 1992-06-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-06-14 | 1995-12-14 | 1996-06-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-06-14 | 1999-12-14 | 2000-06-14 | $7700.00 | Window Closed / Lapsed |