Patent US4748585A successfully refreshed from Google Patents.
US4748585A
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Processor utilizing reconfigurable process segments to accomodate data word length
Assignee: BUELL DUNCAN A
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Filing: 1985-12-26
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Granted: 1988-05-31
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Expires: 2005-12-26
Abstract
Abstract An independently programmable, parallel processor for electronic computers for performing mathematical and logical operations is provided having an array of arithmetic-logic units which are interconnected so as to form dynamically reconfigurable segments of arithmetic-logic units within the array. These dynamically reconfigurable segments are formed by particular combinations of the arithmetic-logic units and are so combined with selective switching circuitry so as to provide the processor with its independent and parallel features.
Inventors
- 👤 Donald M. Chiarulli
- 👤 W. G. Rudd
- 👤 Duncan A. Buell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 12:51
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/57; G06F9/00; G06F9/06; G06F9/22; G06F9/226; G06F9/30; G06F9/30003; G06F9/30007; G06F9/3001; G06F9/30014; G06F9/30072; G06F9/38; G06F9/3885; G06F9/3893; G06F9/3895; G06F9/3897; G06F2207/00; G06F2207/38; G06F2207/3804; G06F2207/3808; G06F2207/3828
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
199 words
A method of operating an electronic computer processor having a plurality of ALU's which may be operated in combination to increase their effective word length comprising the steps of: (a) synchronizing two or more of said ALU's; (b) connecting two or more of said ALU's according to a field in a single instruction word, whereby each group of connected ALU's and each isolated ALU define a segment having a data word length equal to the combined word length of each ALU in said segment; (c) entering a separate operation code and a separate operand instruction for each of said ALU's, said operation codes and said operand instructions being contained in a field in said single instruction word; (d) generating a local status output for each of said ALU's; (e) converting each of said local status outputs to a binary status bit; (f) resolving said binary status bits into a single-bit condition code; (g) selecting a common, next instruction word address for said ALU's based upon a status of a condition enable code which directs whether said selection is to be made unconditionally or whether said selection is to be made conditioned upon a status of said single-bit condition code.
Claim 2
Independent Claim
199 words
A method of operating an electronic computer processor having a plurality of ALU's which may be operated in combination to increase their effective word length comprising the steps of: (a) synchronizing two or more of said ALU's; (b) connecting two or more of said ALU's according to a field in a single instruction word, whereby each group of connected ALU's and each isolated ALU define a segment having a data word length equal to the combined word length of each ALU in said segment; (c) entering a separate operation code and a separate operand instruction for each of said ALU's, said operation codes and said operand instructions being contained in a field in said single instruction word; (d) generating a local status output for each of said ALU's; (e) converting each of said local status outputs to a binary status bit; (f) resolving said binary status bits into a single-bit condition code; (g) selecting a common, next instruction word address for said ALU's based upon a status of a condition enable code which directs whether said selection is to be made unconditionally or whether said selection is to be made conditioned upon a status of said single-bit condition code.
Claim 3
Dependent Claim
21 words
A method according to claim 1 wherein said condition enable code is responsive to a field in said single instruction word.
Claim 4
Dependent Claim
40 words
A method according to claim 2 wherein said conversion of said local status bits is accomplished by operation of a local test mask for each ALU, said local test mask being responsive to a field in said single instruction word.
Claim 5
Dependent Claim
57 words
A processor according to claim 3, wherein: (a) said binary status bits for each segment are resolved into a local condition code for each segment; (b) said local condition codes are resolved into a single-bit condition code by operation of an AND combination or an OR combination in response to a field in said single instruction word.
Claim 6
Dependent Claim
47 words
A method according to claim 4 further comprising the step of entering a branching instruction into a sequencer, said branching instruction being contained in a field in said single instruction word, and said sequencer being in communication with said condition enable code and said single-bit condition code.
Claim 7
Dependent Claim
17 words
A method according to claim 5, wherein there is a single program for all of said ALU's.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-05-31 | 1991-11-30 | 1992-05-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-05-31 | 1995-11-30 | 1996-05-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-05-31 | 1999-11-30 | 2000-05-31 | $7700.00 | Window Closed / Lapsed |