Data transfer apparatus and system

Claim 2

A data transfer system in which a plurality of data transfer apparatuses are adapted for mutual exchange of data, each said apparatus comprising: a computer for processing data, having on one chip a read only memory, a random access memory and an arithmetic logic unit, wherein said arithmetic logic unit processes the plural bits of serial data received through an input port means in accordance with a predetermined program stored in said read only memory, said read only memory stores a serial-to-parallel data conversion program and said arithmetic logic unit takes said plural bits of serial data to store the taken bits of serial data in said random access memory and produces plural bits of parallel data by reading out the bits stored in said random access memory; communication means for receiving data to be processed by said computer from another of said apparatuses; means for setting said apparatus to be a master apparatus or a slave apparatus relative to said other apparatus in data transfer; means operable prior to the reception of the data to be processed from said other apparatus by way of said communication means, for discriminating a characteristic of data transmission by said other apparatus, if said one apparatus is set to be a slave apparatus; and means for controlling the data reception by said communication means in accordance with the characteristic discriminated by said discriminating means so as to render a data reception characteristic of said one apparatus compatible with the discriminated data transmission characteristic of said other apparatus.

Claim 3

A data processing apparatus according to claim 1, wherein said random access memory has a plurality of storage areas each corresponding to one of a plurality of output terminals of said output port means, and said arithmetic logic unit is adapted to store each bit of the data in a predetermined area of said random access memory and then read out the data stored in the areas of said random access memory correspondingly to each output terminal.

Claim 4

A data processing apparatus according to claim 8, wherein said input port means receives the plural bits of serial data through a transmission line.

Claim 5

A data transfer system according to claim 1, wherein said discriminating means is arranged to detect a parameter of a primary synchronizing signal transmitted to said data transfer apparatus from said other apparatus and wherein said controlling means is arranged to control data communication with said other apparatus in accordance with said parameter.

Claim 6

A data transfer apparatus according to claim 4, further comprising means for generating a return synchronizing signal for return transmission to said other apparatus, the parameter of said return synchronizing signal which corresponds with said detected parameter of said primary synchronizing signal being set according to said detected parameter.

Claim 7

A data transfer apparatus according to claim 4 or claim 5, wherein said detected parameter is the pulse period of a clock pulse train constituting said primary synchronizing signal and wherein said controlling means is arranged to synchronize data reception of multi-bit data signals of which the bit length corresponds with the pulse period of said primary synchronizing signal, in accordance with said detected pulse length thereof.

Claim 8

A data transfer system according to claim 1, wherein said discriminating means discriminates a data transmission speed of said other apparatus.

Claim 9

A data processing apparatus adapted to exchange data with another apparatus, comprising: input port means having a plurality of input terminals adapted to enter respective bits of data in parallel; a computer for processing having on one chip a read only memory, a random access memory and an arithmetic logic unit, wherein said arithmetic logic unit processes the bits of data entered in parallel through said input port means in accordance with a predetermined program stored in said read only memory, said read only memory stores a parallel-to-serial data conversion program, and said arithmetic logic unit takes said bits of parallel data into said computer to store the in-taken bits of parallel data in said random access memory and produces bits of serial data by reading out bits stored in said random access memory bit by bit, in accordance with said conversion program; and output means adapted to transmit the bits of serial data produced by said computer to said other apparatus; communication means for receiving data to be processed by said computer from said apparatus; means for setting said apparatus to be a master apparatus or a slave apparatus relative to said other apparatus in data transfer; means operable prior to the reception of the data to be processed from said other apparatus by way of said communication means, for discriminating a characteristic of data transmission by said other apparatus, if said one apparatus is set to be a slave apparatus; and means for controlling the data reception by said communication means in accordance with the characteristic discriminated by said discriminating means so as to render a data reception characteristic of said one apparatus compatible with the discriminated data transmission characteristic of said other apparatus.

Claim 10

A data processing apparatus adapted to exchange data with another apparatus, comprising: input port means having a plurality of input terminals adapted to enter respective bits of data in parallel; a computer for processing having on one chip a read only memory, a random access memory and an arithmetic logic unit, wherein said arithmetic logic unit processes the bits of data entered in parallel through said input port means in accordance with a predetermined program stored in said read only memory, said read only memory stores a parallel-to-serial data conversion program, and said arithmetic logic unit takes said bits of parallel data into said computer to store the in-taken bits of parallel data in said random access memory and produces bits of serial data by reading out bits stored in said random access memory bit by bit, in accordance with said conversion program; and output means adapted to transmit the bits of serial data produced by said computer to said other apparatus; communication means for receiving data to be processed by said computer from said apparatus; means for setting said apparatus to be a master apparatus or a slave apparatus relative to said other apparatus in data transfer; means operable prior to the reception of the data to be processed from said other apparatus by way of said communication means, for discriminating a characteristic of data transmission by said other apparatus, if said one apparatus is set to be a slave apparatus; and means for controlling the data reception by said communication means in accordance with the characteristic discriminated by said discriminating means so as to render a data reception characteristic of said one apparatus compatible with the discriminated data transmission characteristic of said other apparatus.

Claim 11

A data processing apparatus according to claim 8, wherein said random access memory has a plurality of storage areas each corresponding to one of said plurality of input termials of said input port means, and said arithmetic logic unit is adapted to store each bit of the data in a predetermined area of said random access memory and then read out the data stored in the areas of said random access memory in a predetermined order.

Claim 12

A data processing apparatus according to claim 8, wherein said output means transmits the bits of serial data at a predetermined speed.

Claim 13

A data processing apparatus according to claim 8, wherein said output means transmits the bits of serial data through a transmission line.