Patent US4746965A successfully refreshed from Google Patents.
US4746965A
Expired / Lapsed
US
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Integrated semiconductor circuit device
Assignee: Toshiba Corp
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Filing: 1985-11-18
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Granted: 1988-05-24
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Expires: 2005-11-18
Abstract
Abstract Disclosed is an integrated semiconductor circuit device which has a plurality of cell arrays formed in parallel on a surface region of the substrate, and a three-layer wire formed on the substrate and between each cell array. The direction of a wire track of a second layer wire is originally determined in a direction parallel to the cell arrays, and the direction of wire tracks of first and third layer wires is originally determined in a direction orthogonal to the originally determined direction of the wire track of the second layer wire. The first layer wire and the third layer wire are formed on the same wire track. Part of the third layer wire is formed on a wire track orthogonal to the originally determined direction of the wire track of the third layer, and the third layer wire and the second layer wire are connected to each other on the wire track which is orthogonal to the originally determined direction of the wire track of the third layer wire.
Inventors
- 👤 Hiroaki Nishi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 15:18
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/43
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
180 words
An integrated semiconductor circuit device comprising: (a) a semiconductor substrate; (b) a plurality of cell arrays formed in parallel on said substrate; (c) wiring formed in at least first, second and third wiring layers on said substrate for connecting said cell arrays, each layer including wires arranged in predetermined parallel wire tracks, the direction of a wire track of a second layer wire being originally determined in a first direction parallel to the cell arrays, the direction of a wire track of first and third layer wires being originally determined in a second direction orthogonal to the first direction, said first layer wire and said third layer wire overlapping each other, one of said first layer wire and said overlapping third layer wire having a bent portion formed on a wire track orthogonal to the second direction, and said one of said first layer wire and said overlapping third layer wire at said bent portion, and the other of said first and third layer wires, connected to respective second layer wires on the same wire track of said first direction.
Claim 2
Dependent Claim
180 words
An integrated semiconductor circuit device comprising: (a) a semiconductor substrate; (b) a plurality of cell arrays formed in parallel on said substrate; (c) wiring formed in at least first, second and third wiring layers on said substrate for connecting said cell arrays, each layer including wires arranged in predetermined parallel wire tracks, the direction of a wire track of a second layer wire being originally determined in a first direction parallel to the cell arrays, the direction of a wire track of first and third layer wires being originally determined in a second direction orthogonal to the first direction, said first layer wire and said third layer wire overlapping each other, one of said first layer wire and said overlapping third layer wire having a bent portion formed on a wire track orthogonal to the second direction, and said one of said first layer wire and said overlapping third layer wire at said bent portion, and the other of said first and third layer wires, connected to respective second layer wires on the same wire track of said first direction.
Claim 3
Dependent Claim
182 words
An integrated semiconductor circuit device comprising: (a) a semiconductor substrate; (b) a plurality of cell arrays formed in parallel on said substrate; (c) wiring formed in at least first, second and third wiring layers on said substrate for connecting said cell arrays, each layer including wires arranged in predetermined parallel wire tracks, the direction of a wire track of a second layer wire being originally determined in a first direction parallel to the cell arrays, the direction of a wire track of first and third layer wires being originally determined in a second direction orthogonal to the first direction, said first layer wire and said third layer wire overlapping each other, one of said first layer wire and said overlapping third layer wire having a bent portion formed on a wire track orthogonal to the second direction, and said one of said first layer wire and said overlapping third layer wire at said bent portion, and the other of said first and third layer wires, connected to each other through said second layer wire on a single track of said first direction.
Claim 4
Dependent Claim
182 words
An integrated semiconductor circuit device comprising: (a) a semiconductor substrate; (b) a plurality of cell arrays formed in parallel on said substrate; (c) wiring formed in at least first, second and third wiring layers on said substrate for connecting said cell arrays, each layer including wires arranged in predetermined parallel wire tracks, the direction of a wire track of a second layer wire being originally determined in a first direction parallel to the cell arrays, the direction of a wire track of first and third layer wires being originally determined in a second direction orthogonal to the first direction, said first layer wire and said third layer wire overlapping each other, one of said first layer wire and said overlapping third layer wire having a bent portion formed on a wire track orthogonal to the second direction, and said one of said first layer wire and said overlapping third layer wire at said bent portion, and the other of said first and third layer wires, connected to each other through said second layer wire on a single track of said first direction.
Claim 5
Dependent Claim
158 words
An integrated semiconductor circuit device comprising: (a) a semiconductor substrate; (b) a plurality of cell arrays formed in parallel on said substrate; (c) wiring formed in at least first, second and third wiring layers on said substrate for connecting said cell arrays, each layer including wires arranged in predetermined parrallel wire tracks, the direction of a wire track of a second layer wire being originally determined in a first direction parallel to the cell arrays, the direction of a wire track of first and third layer wires being originally determined in a second direction orthogonal to the first direction, said first layer wire and said third layer wire overlapping each other, said second wiring layer including a second layer wire arranged orthogonal to said first direction, and said first layer wire and said overlapping third layer wire connected to each other through respective connections to different portions of said second layer wire arranged orthogonal to said first direction.
Claim 6
Dependent Claim
158 words
An integrated semiconductor circuit device comprising: (a) a semiconductor substrate; (b) a plurality of cell arrays formed in parallel on said substrate; (c) wiring formed in at least first, second and third wiring layers on said substrate for connecting said cell arrays, each layer including wires arranged in predetermined parrallel wire tracks, the direction of a wire track of a second layer wire being originally determined in a first direction parallel to the cell arrays, the direction of a wire track of first and third layer wires being originally determined in a second direction orthogonal to the first direction, said first layer wire and said third layer wire overlapping each other, said second wiring layer including a second layer wire arranged orthogonal to said first direction, and said first layer wire and said overlapping third layer wire connected to each other through respective connections to different portions of said second layer wire arranged orthogonal to said first direction.
Claim 7
Dependent Claim
19 words
An integrated semiconductor circuit device according to claim 1, in which said wiring is formed between said cell arrays.
Claim 8
Dependent Claim
19 words
An integrated semiconductor circuit device according to claim 2, in which said wiring is formed between said cell arrays.
Claim 9
Dependent Claim
19 words
An integrated semiconductor circuit device according to claim 3, in which said wiring is formed between said cell arrays.
Claim 10
Dependent Claim
24 words
An integrated semiconductor circuit device according to claim 1, in which said first, second and third wiring layers are sequentially formed on said substrate.
Claim 11
Dependent Claim
24 words
An integrated semiconductor circuit device according to claim 2, in which said first, second and third wiring layers are sequentially formed on said substrate.
Claim 12
Dependent Claim
24 words
An integrated semiconductor circuit device according to claim 3, in which said first, second and third wiring layers are sequentially formed on said substrate.
Claim 13
Dependent Claim
29 words
An integrated semiconductor circuit device according to claim 1, in which said first layer is made of polycrystalline silicon and said second and third layers are made of aluminum.
Claim 14
Dependent Claim
29 words
An integrated semiconductor circuit device according to claim 2, in which said first layer is made of polycrystalline silicon and said second and third layers are made of aluminum.
Claim 15
Dependent Claim
29 words
An integrated semiconductor circuit device according to claim 3, in which said first layer is made of polycrystalline silicon and said second and third layers are made of aluminum.
Claim 16
Dependent Claim
18 words
An integrated circuit semiconductor circuit device according to claim 1, in which said cell arrays are standard cells.
Claim 17
Dependent Claim
18 words
An integrated circuit semiconductor circuit device according to claim 2, in which said cell arrays are standard cells.
Claim 18
Dependent Claim
17 words
An integrated semiconductor circuit device according to claim 3, in which said cell arrays are standard cells.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-05-24 | 1991-11-23 | 1992-05-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-05-24 | 1995-11-23 | 1996-05-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-05-24 | 1999-11-23 | 2000-05-24 | $7700.00 | Window Closed / Lapsed |