US4746874A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit layout for signal amplification
Assignee: Telefunken Electronic GmbH
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Filing: 1986-10-07
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Granted: 1988-05-24
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Expires: 2006-10-07
Abstract
Abstract In a circuit layout for signal amplification with the aid of a differential amplifier and signal coupling via a first capacitor, it is proposed, in order to prevent unacceptable operating point displacements into the non-linear area of the amplifier layout in the event of temporarily interfering high-level signals, that one input of the differential amplifier connected to the signal source via the first capacitor be connected via a first resistor, and the other input via a second resistor, jointly via an electronic switch controllable by a comparator, to reference potential. A reference voltage source is connected to one input of the comparator, and the signal source to the other input of the comparator via an RC element, whose time constant is of the same order of magnitude as the time constant formed by the first capacitor and the first resistor.
Inventors
- 👤 Gerhard Forster
- 👤 Konrad Hirsch
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 15:51
CPC Classifications
H; H03; H03F; H03F1/00; H03F1/32; H03F1/3211; H03G; H03G3/00; H03G3/20; H03G3/30; H03G3/34; H03G3/345
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
218 words
A circuit layout for signal amplification by means of a differential amplifier (DV1) and a first capacitor (9) at one of its two inputs for signal coupling, wherein one input of the differential amplifier (DV1) to which the first capacitor (9) is connected, is connected via a first resistor (5), and the other input of the differential amplifier (DV1) is connected via a second resistor (6), jointly via an electronic switch (8), to reference potential (M), the electronic switch (8) is controllable by a comparator (12), a reference voltage source (U 13 ) is connected to one input of the comparator (12) and an RC element (11, 10) to the other input, the resistor (11) of the RC element is connected to reference potential (M) and the capacitor (10) of the RC element to the input (E) of the circuit layout, the time constant of the RC element (10, 11) of the comparator (12) is of the same order of magnitude as the product of the capacitance of the first capacitor (9) and the resistance value of the first resistor (5), and the time constant formed by the first capacitor (9) and the first resistor (5) is substantially smaller than the time constant formed by the first capacitor (9) and the input resistance of the differential amplifier (DV1).
Claim 2
Dependent Claim
218 words
A circuit layout for signal amplification by means of a differential amplifier (DV1) and a first capacitor (9) at one of its two inputs for signal coupling, wherein one input of the differential amplifier (DV1) to which the first capacitor (9) is connected, is connected via a first resistor (5), and the other input of the differential amplifier (DV1) is connected via a second resistor (6), jointly via an electronic switch (8), to reference potential (M), the electronic switch (8) is controllable by a comparator (12), a reference voltage source (U 13 ) is connected to one input of the comparator (12) and an RC element (11, 10) to the other input, the resistor (11) of the RC element is connected to reference potential (M) and the capacitor (10) of the RC element to the input (E) of the circuit layout, the time constant of the RC element (10, 11) of the comparator (12) is of the same order of magnitude as the product of the capacitance of the first capacitor (9) and the resistance value of the first resistor (5), and the time constant formed by the first capacitor (9) and the first resistor (5) is substantially smaller than the time constant formed by the first capacitor (9) and the input resistance of the differential amplifier (DV1).
Claim 3
Dependent Claim
134 words
A circuit layout according to claim 1, wherein the differential amplifier (first differential amplifier DV1) contains two transistors (1, 2) with a common emitter current source (7) and with identically sized collector resistors (3, 4), a second differential amplifier (DV2) with two transistors (15, 16) is coupled to the collectors of the two transistors (1, 2) of the first differential amplifier (DV1), a second emitter current source (20) is provided for the two transistors (15, 16) of the second differential amplifier (DV2), said source (20) being connectable via a change switch (18, 19) controlled by the comparator (12) to the interconnected emitters of both transistors (15, 16) of the second differential amplifier (DV2) in a first switching condition and to the output (A') of the second differential amplifier (DV2) in a second switching condition.
Claim 4
Dependent Claim
157 words
Circuit layout according to claim 2, wherein the common emitter current source (7) and the second emitter current source (20) are designed as controllable current sources and the amplification of the signal amplifier formed by the first and second differential amplifiers (DV1, DV2) is settable by mans of the controllable current sources (7, 20), a first preamplifier (30) is connected upstream of the signal input of the comparator (12) and a second preamplifier (31) upstream of the reference input of comparator (12), both preamplifiers (30, 31) are controllable in respect of amplification in the same way as the signal amplifier (DV1, DV2), the maximum output voltage of preamplifier (30) is identical to that of the signal amplifier (DV1, DV2) and that of preamplifier (31) is slightly smaller than that of the signal amplifier (DV1, DV2) and the output (13) of preamplifier (31) is held in the limit condition via its input (33) regardless of the amplification setting.
Claim 5
Dependent Claim
48 words
A circuit layout according to claim 2, wherein an emitter follower (22, 23) is connected upstream of the transistors, (1, 2) of the first differential amplifier (DV1), and the first and second resistors (5, 6) are connected to the respective base electrodes of the emitter followers (22, 23).
Claim 6
Dependent Claim
71 words
A circuit layout according to claim 4, wherein an additional transistor (24) is connected into the collector line of an emitter follower (22), the basis of said transistor being connected to a current mirror circuit (26) connected to the current supply line (+U B ) of the collector, and the collector of the current mirror circuit (26) carrying the mirrored current is connected to the base of the emitter follower (22).
References Cited (Backward Citations)
US3872247A
Cited
US4300102A
Cited
GB2027306A
Cited
US4464632A
Cited
US4405901A
Cited
US4527128A
Cited
GB2151887A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-05-24 | 1991-11-23 | 1992-05-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-05-24 | 1995-11-23 | 1996-05-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-05-24 | 1999-11-23 | 2000-05-24 | $7700.00 | Window Closed / Lapsed |