US4527128A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Bistate linear amplifier circuit
Assignee: National Semiconductor Corp
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Filing: 1983-09-06
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Granted: 1985-07-02
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Expires: 2003-09-06
Abstract
Abstract A linear amplifier output stage is provided with unity gain buffer means having an input coupled to the output terminal and an output coupled to the stage input. The unity gain buffer means is normally turned off by a control signal. When the amplifier is disabled by switching its bias current off, the buffers are turned on so that the output stage input capacitance is charged or discharged via the buffer means in accordance with the output terminal signal. When a plurality of such amplifiers are commonly coupled to a signal line the off amplifiers cannot be driven into conduction by the operating amplifier's output signal.
Inventors
- 👤 Harry J. Bittner
- 👤 Daniel D. Culmer
- 👤 Walter R. Davis
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 01:19
CPC Classifications
H; H03; H03F; H03F1/00; H03F1/30; H03F1/303
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
126 words
A linear amplifier output stage circuit, adapted for coupling to a load element in common with one or more additional amplifiers, said output stage having input and output terminals and at least one output transistor connected to produce an amplified output signal at said output terminal in response to a signal at said input terminal, said circuit comprising: means for providing operating bias current for said output transistor; means for turning said operating bias current on and off in response to a control signal; unity gain buffer amplifier means having an input coupled to said output terminal and an output coupled to said output stage input terminal; and means for turning said buffer amplifier means on and off in complementary fashion with said operating bias current.
Claim 2
Dependent Claim
126 words
A linear amplifier output stage circuit, adapted for coupling to a load element in common with one or more additional amplifiers, said output stage having input and output terminals and at least one output transistor connected to produce an amplified output signal at said output terminal in response to a signal at said input terminal, said circuit comprising: means for providing operating bias current for said output transistor; means for turning said operating bias current on and off in response to a control signal; unity gain buffer amplifier means having an input coupled to said output terminal and an output coupled to said output stage input terminal; and means for turning said buffer amplifier means on and off in complementary fashion with said operating bias current.
Claim 3
Dependent Claim
25 words
The circuit of claim 1 wherein said unity gain buffer amplifier comprises an emitter follower transistor having a constant current device in its emitter circuit.
Claim 4
Dependent Claim
28 words
The circuit of claim 2 wherein said means for turning said buffer amplifier means on and off comprise means for controlling the conduction of said constant current device.
Claim 5
Dependent Claim
53 words
The circuit of claim 1 wherein said output stage comprises a complementary pair of output transistors and said unity gain buffer amplifier means comprise first and second complementary emitter followers each one having its input coupled to said output terminal and respective outputs coupled to the inputs of said pair of output transistors.
Claim 6
Dependent Claim
33 words
The circuit of claim 4 further comprising a gain stage having an output coupled to drive said pair of output transistor, an input, and means for providing bias current for said gain stage.
Claim 7
Dependent Claim
47 words
The circuit of claim 5 further comprising a third emitter follower having an input coupled to said gain stage output, an output coupled to said gain stage input, and means for turning said third emitter follower on and off in complementary fashion with said operating bias current.
References Cited (Backward Citations)
US3737798A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-07-01 | 1988-12-31 | 1989-07-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-07-01 | 1992-12-31 | 1993-07-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-07-01 | 1996-12-31 | 1997-07-02 | $7700.00 | Window Closed / Lapsed |