US4464632A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Volume control circuit
Assignee: Toshiba Corp
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Filing: 1981-06-19
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Granted: 1984-08-07
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Expires: 2001-06-19
Abstract
Abstract A volume control circuit is provided which is not influenced by power supply fluctuations and which eliminates the audio signal component when the circuit is adjusted to minimum volume. An audio input signal is amplified by a differential amplifier and supplied to a substantially doubly balanced differential amplifier. Gain control of the audio signal is achieved by adjusting the bias voltage of the doubly balanced differential amplifier. The collector electrodes of two transistors used during minimum volume operation are connected directly to a power supply line. The controlled audio signal is supplied from the doubly balanced differential amplifier to a current mirror circuit which functions to cancel fluctuations in the power source. The connection of the collector electrodes of the two transistors in the doubly balanced differential amplifier to the power supply line functions to eliminate an audio component on the output when the volume control is set to minimum volume.
Inventors
- 👤 Kozo Yoshihisa
- 👤 Isamu Okui
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 18:59
CPC Classifications
H; H03; H03G; H03G3/00; H03G3/02; H03G3/04; H03G3/10; H03G1/00; H03G1/0005; H03G1/0017; H03G1/0023
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
360 words
A volume control circuit having a pair of reference potential lines, an input terminal and an output terminal, said volume control circuit comprising: a differential amplifier comprising first and second transistors, the emitter electrode of said first transistor being connected to the emitter electrode of said second transistor through a resistor and to one of said reference potential lines through a first constant current source, the emitter electrode of said second transistor being connected to said one reference potential line through a second constant current source; a substantially doubly balanced differential amplifier comprising third, fourth, fifth and sixth transistors, the emitter electrodes of said third and fourth transistors being connected in common to the collector electrode of said first transistor, the emitter electrodes of said fifth and sixth transistors being connected in common to the collector electrode of said second transistor, the collector electrodes of said fourth and fifth transistors being connected in common to the other reference potential line; a variable reference voltage source having a pair of terminals, one of the terminals being connected to the base electrodes of said third and sixth transistors, the other terminal being connected to said one reference potential line; a fixed reference voltage source having a pair of terminals, one of the terminals being connected to the base electrodes of said fourth and fifth transistors, the other terminal being connected to said one reference potential line; and a current mirror circuit comprising seventh and eighth transistors, the emitter electrode of said seventh transistor being connected to the collector electrode of said third transistor and coupled to said other reference potential line, the emitter electrode of said eighth transistor being connected to the collector electrode of said sixth transistor and coupled to said other reference potential line, the base electrodes of said seventh and eighth transistors and the collector electrode of said eighth transistor being connected in common, the collector electrode of said seventh transistor being connected to said one reference potential line through a resistor and coupled to said output terminal, the collector electrode of said eighth transistor being connected to said one reference potential line through a third constant current source.
Claim 2
Dependent Claim
360 words
A volume control circuit having a pair of reference potential lines, an input terminal and an output terminal, said volume control circuit comprising: a differential amplifier comprising first and second transistors, the emitter electrode of said first transistor being connected to the emitter electrode of said second transistor through a resistor and to one of said reference potential lines through a first constant current source, the emitter electrode of said second transistor being connected to said one reference potential line through a second constant current source; a substantially doubly balanced differential amplifier comprising third, fourth, fifth and sixth transistors, the emitter electrodes of said third and fourth transistors being connected in common to the collector electrode of said first transistor, the emitter electrodes of said fifth and sixth transistors being connected in common to the collector electrode of said second transistor, the collector electrodes of said fourth and fifth transistors being connected in common to the other reference potential line; a variable reference voltage source having a pair of terminals, one of the terminals being connected to the base electrodes of said third and sixth transistors, the other terminal being connected to said one reference potential line; a fixed reference voltage source having a pair of terminals, one of the terminals being connected to the base electrodes of said fourth and fifth transistors, the other terminal being connected to said one reference potential line; and a current mirror circuit comprising seventh and eighth transistors, the emitter electrode of said seventh transistor being connected to the collector electrode of said third transistor and coupled to said other reference potential line, the emitter electrode of said eighth transistor being connected to the collector electrode of said sixth transistor and coupled to said other reference potential line, the base electrodes of said seventh and eighth transistors and the collector electrode of said eighth transistor being connected in common, the collector electrode of said seventh transistor being connected to said one reference potential line through a resistor and coupled to said output terminal, the collector electrode of said eighth transistor being connected to said one reference potential line through a third constant current source.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-08-07 | 1988-02-06 | 1988-08-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-08-07 | 1992-02-06 | 1992-08-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-08-07 | 1996-02-06 | 1996-08-07 | $7700.00 | Window Closed / Lapsed |