US4746823A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Voltage-insensitive and temperature-compensated delay circuit for a monolithic integrated circuit
Assignee: Dallas Semiconductor Corp
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Filing: 1986-07-02
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Granted: 1988-05-24
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Expires: 2006-07-02
Abstract
Abstract A delay circuit which is insensitive to variations in power supply voltage, which is temperature-compensated, and which is suitable for fabrication in a monolithic integrated circuit includes circuitry for charging a capacitive element through a resistive element from GND toward the power supply voltage. The voltage across the capacitive element is compared to a reference voltage by a voltage comparator, and the voltage comparator generates an output signal when the voltage on the capacitor becomes greater than the reference voltage. The reference voltage for the comparator is generated by a resistor divider connected between GND and the power supply voltage. Inasmuch as the reference voltage varies with changes in the power supply voltage in such a manner as to be maintained at a substantially fixed percentage of the power supply voltage, the time delay provided by the delay circuit is essentially independent of variations in power supply voltage. By utilizing resistors in the resistor divider that have differing temperature coefficients of resistance, the reference voltage for the comparator can be increased and decreased in a predetermined manner in response to increases and decreases in ambient temperature, allowing the time delay of the delay circuit to be adjusted in a predetermined manner as a function of temperature.
Inventors
- 👤 Robert D. Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 23:05
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/01; H03K5/04
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
324 words
A delay circuit fabricated in a monolithic integrated circuit, said delay circuit having an input node for receiving an input signal, having a first DC reference voltage node for receiving a first DC reference voltage, having a second DC reference voltage node for receiving a second DC reference voltage, and having a first internal signal node, a second internal signal node, and an output node, comprising: a. means responsive to a logic state transition of said input signal for providing a signal on said first internal signal node that transitions substantially from said first DC reference voltage to said second DC reference voltage; b. a first resistive element connected between said first internal signal node and said second internal signal node; c. a capacitive element connected between said second internal signal node and said first DC reference voltage node; d. voltage divider means coupled between said first DC reference voltage node and said second DC voltage reference node for generating on a third DC voltage reference node a third DC reference voltage having a value equal to said first DC reference voltage plus a substantially fixed percentage of the voltage difference between said first and second DC reference voltages; and e. a voltage comparator having two inputs and an output, one of said voltage comparator inputs being connected to said second internal signal node, the other of said voltage comparator inputs being coupled to said third DC reference voltage node, the output of said voltage comparator being coupled to the output node of said delay circuit, said voltage comparator generating a logic state transition on its output when the voltage on said second internal signal node transitions from being less than said third DC reference voltage to greater than said third DC reference voltage; whereby a delay output signal may be provided and whereby the amount of delay is substantially independent of variations in the voltage difference between said first and second reference voltages.
Claim 2
Dependent Claim
324 words
A delay circuit fabricated in a monolithic integrated circuit, said delay circuit having an input node for receiving an input signal, having a first DC reference voltage node for receiving a first DC reference voltage, having a second DC reference voltage node for receiving a second DC reference voltage, and having a first internal signal node, a second internal signal node, and an output node, comprising: a. means responsive to a logic state transition of said input signal for providing a signal on said first internal signal node that transitions substantially from said first DC reference voltage to said second DC reference voltage; b. a first resistive element connected between said first internal signal node and said second internal signal node; c. a capacitive element connected between said second internal signal node and said first DC reference voltage node; d. voltage divider means coupled between said first DC reference voltage node and said second DC voltage reference node for generating on a third DC voltage reference node a third DC reference voltage having a value equal to said first DC reference voltage plus a substantially fixed percentage of the voltage difference between said first and second DC reference voltages; and e. a voltage comparator having two inputs and an output, one of said voltage comparator inputs being connected to said second internal signal node, the other of said voltage comparator inputs being coupled to said third DC reference voltage node, the output of said voltage comparator being coupled to the output node of said delay circuit, said voltage comparator generating a logic state transition on its output when the voltage on said second internal signal node transitions from being less than said third DC reference voltage to greater than said third DC reference voltage; whereby a delay output signal may be provided and whereby the amount of delay is substantially independent of variations in the voltage difference between said first and second reference voltages.
Claim 3
Dependent Claim
45 words
The delay circuit according to claim 1 wherein said first resistive element is a network comprising a plurality of resistors and a plurality of laser-fusible links wherein the resistance of said first resistive element can be increased by the selective opening of said laser-fusible links.
Claim 4
Dependent Claim
43 words
The delay circuit according to claim 1 wherein said capacitive element is a network comprising a plurality of capacitors and a plurality of laser-fusible links wherein the capacitance of said capacitive element can be decreased by the selective opening of said laser-fusible links.
Claim 5
Dependent Claim
29 words
The delay circuit according to claim 1 further including means responsive to said input signal and connected in parallel with said capacitive element for rapidly discharging said capacitive element.
Claim 6
Dependent Claim
51 words
The delay circuit according to claim 1 wherein said means for generating a third DC reference voltage comprises second and third resistive elements coupled in series between said first and second DC reference voltage nodes, said third DC reference voltage node comprising a node between said second and third resistive elements.
Claim 7
Dependent Claim
28 words
The delay circuit according to claim 5 wherein the resistances of said second and third resistive elements are separately increasingly adjustable by the selective opening of laser-fusible links.
Claim 8
Dependent Claim
305 words
A delay circuit fabricated in a monolithic integrated circuit, said delay circuit having an input node for receiving an input signal, having a first DC reference voltage node for receiving a first DC reference voltage, having a second DC reference voltage node for receiving a second DC reference voltage, and having a first internal signal node, a second internal signal node, and an output node, comprising: a. means responsive to a logic state transition of said input signal for providing a signal on said first internal signal node that transitions substantially from said first DC reference voltage to said second DC reference voltage; b. a first resistive element connected between said first internal signal node and said second internal signal node; c. a capacitive element connected between said second internal signal node and said first DC reference voltage node; d. voltage divider means coupled between said first DC reference voltage node and said second DC voltage reference node for generating on a third DC voltage reference node a third DC reference voltage intermediate in value between said first and second reference voltages and increasing and decreasing in value in a predetermined manner in response to increases and decreases in the ambient temperature; and e. a voltage comparator having two inputs and an output, one of said voltage comparator inputs being connected to said second internal signal node, the other of said voltage comparator inputs being coupled to said third DC reference voltage node, the output of said voltage comparator being coupled to the output node of said delay circuit, said voltage comparator generating a logic state transition on its output when the voltage on said second internal signal node transitions from being less than said third DC reference voltage to greater than said third DC reference voltage; whereby a temperature-compensated delayed output may be provided.
Claim 9
Dependent Claim
305 words
A delay circuit fabricated in a monolithic integrated circuit, said delay circuit having an input node for receiving an input signal, having a first DC reference voltage node for receiving a first DC reference voltage, having a second DC reference voltage node for receiving a second DC reference voltage, and having a first internal signal node, a second internal signal node, and an output node, comprising: a. means responsive to a logic state transition of said input signal for providing a signal on said first internal signal node that transitions substantially from said first DC reference voltage to said second DC reference voltage; b. a first resistive element connected between said first internal signal node and said second internal signal node; c. a capacitive element connected between said second internal signal node and said first DC reference voltage node; d. voltage divider means coupled between said first DC reference voltage node and said second DC voltage reference node for generating on a third DC voltage reference node a third DC reference voltage intermediate in value between said first and second reference voltages and increasing and decreasing in value in a predetermined manner in response to increases and decreases in the ambient temperature; and e. a voltage comparator having two inputs and an output, one of said voltage comparator inputs being connected to said second internal signal node, the other of said voltage comparator inputs being coupled to said third DC reference voltage node, the output of said voltage comparator being coupled to the output node of said delay circuit, said voltage comparator generating a logic state transition on its output when the voltage on said second internal signal node transitions from being less than said third DC reference voltage to greater than said third DC reference voltage; whereby a temperature-compensated delayed output may be provided.
Claim 10
Dependent Claim
67 words
The delay circuit according to claim 7 wherein said means for generating a third DC reference voltage comprises a second resistive element coupled in series with a third resistive element between said first and second DC reference voltage nodes, said third DC reference voltage node comprising a node between said second and third resistive elements, said second and third resistive elements having differing temperature coefficients of resistance.
Claim 11
Dependent Claim
132 words
The delay circuit according to claim 8 wherein: a. said second resistive element is comprised of a plurality of P-well resistors, a first plurality of polysilicon resistors having temperature coefficients of resistance differing from that of said P-well resistors, and a first plurality of laser-fusible links, said pluralities of resistors and laser-fusible links being interconnected in a first network wherein the resistance and temperature coefficient of resistance of said first resistive element can be selected by the selective opening of said first plurality of laser-fusible links; and b. said third resistive element comprises a second network of a second plurality of polysilicon resistors and a second plurality of laser-fusible links wherein the resistance of said second resistive element can be selected by the selective opening of said second plurality of laser-fusible links.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-05-24 | 1991-11-23 | 1992-05-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-05-24 | 1995-11-23 | 1996-05-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-05-24 | 1999-11-23 | 2000-05-24 | $7700.00 | Window Closed / Lapsed |