Method of making complementary GaAs heterojunction transistors

Claim 2

A planar process for fabricating at least one n-type MESFET transistor and at least one p-type MODFET transistor comprising: forming a first layer of intrinsic GaAs of a thickness of from about 1 to about 5 microns on a first surface of a semi-insulating wafer by molecular beam epitaxy (MBE); forming a second layer of updoped AlGaAs of a thickness of from about 50 to about 100 Angstroms atop the first layer by MBE; forming a third layer of p-type AlGaAs of a thickness of from about 300 to about 500 Angstroms atop the second layer by MBE; forming a fourth cap layer of p+ AlGaAs having a p-type impurity concentratin of about 10 18 cm -3 atop the third layer by MBE; establishing the channel region of the n-type transistor by ion implantation of n-type impurity ions through a fifth layer of Si 3 N 4 of about 500 to about 1,000 Angstroms thickness to establish the channel in the first layer of gallium arsenide; striping away the fifth layer; laying down gate electrodes of a refractory metal compound for the n- and p-type transistors; establishing source and drain regions for the n- and p-type transistors by ion implatation of respective n- and p-type impurities through a sixth Si 3 N 4 layer having an effective thickness similar to the fifth layer; annealing the structure at about 800° C. for about 1-10 minutes; and depositing electrode metallizations atop the respective source and drain regions of the n- and p-type transistor.

Claim 3

The process of claim 1 wherein the wafer is a silicon wafer.

Claim 4

The process of claim 1 wherein the wafer is a GaAs wafer.

Claim 5

The process of claim 1 wherein the relative proportions of Al and Ga in the AlGaAs layers are defined by the formulate Al x Ga 1-x As where x is at least 0.3.

Claim 6

The process of claim 1 further including a proton bombardment step in which protons of sufficient energy to form a high resistivity region are introduced into and through all of the layers overlaying the semi-insulating layer and penetrating an effective distance into the semi-insulating layer through a window in a photoresist layer which is implaced atop the transistor structures, the window opening being between an n-type transistor and a p-type transistor.

Claim 7

A partially planar process for fabricating at least one n-type MESFET transistor and at least one p-type MODFET transistor comprising: forming a first layer of intrinsic GaAs of a thickness of from about 1 to about 5 microns on a first surface of a semi-insulating wafer by molecular beam epitaxy (MBE); forming a second layer of undoped AlGaAs of a thickness of from about 50 to about 100 Angstroms atop the first layer by MBE; forming a third layer of p-type AlGaAs of a thickness of from about 300 to about 500 Angstroms atop the second layer by MBE; forming a fourth cap alyer of p+ AlGaAs having a p-type impurity concentration of about 10 18 cm -3 atop the third layer by MBE; establishing the channel region of the n-type transistor by ion implantation on n-type impurity ions through a fifth layer of Si 3 N 4 of about 500 to about 1,000 Angstroms thickness to establish the channel in the first layer of gallium arsenide; striping away the fifth layer; forming gate electrodes of a refractory metal compound for the n- and p-type transistors; etching away all of the fourth cap layer, the third layer, the second layer and the first layer down to the first surface of the semi-insulating area in all areas except those directly underneath the gate electrode of the refractory metal compound for the n- and p-type transistors; establishing source and drain regions for the n- and p-type transistors by ion implantation of respective n- and p-type impurities through a sixth Si 3 N 4 layer having an effective thickness similar to the fifth layer; annealing the structure at about 800° C. for about 1-10 minutes; and depositing electrode metallizations atop the respective source and drain regions of the n- and p-type transistors.

Claim 8

A partially planar process for fabricating at least one n-type MESFET transistor and at least one p-type MODFET transistor comprising: forming a first layer of intrinsic GaAs of a thickness of from about 1 to about 5 microns on a first surface of a semi-insulating wafer by molecular beam epitaxy (MBE); forming a second layer of undoped AlGaAs of a thickness of from about 50 to about 100 Angstroms atop the first layer by MBE; forming a third layer of p-type AlGaAs of a thickness of from about 300 to about 500 Angstroms atop the second layer by MBE; forming a fourth cap alyer of p+ AlGaAs having a p-type impurity concentration of about 10 18 cm -3 atop the third layer by MBE; establishing the channel region of the n-type transistor by ion implantation on n-type impurity ions through a fifth layer of Si 3 N 4 of about 500 to about 1,000 Angstroms thickness to establish the channel in the first layer of gallium arsenide; striping away the fifth layer; forming gate electrodes of a refractory metal compound for the n- and p-type transistors; etching away all of the fourth cap layer, the third layer, the second layer and the first layer down to the first surface of the semi-insulating area in all areas except those directly underneath the gate electrode of the refractory metal compound for the n- and p-type transistors; establishing source and drain regions for the n- and p-type transistors by ion implantation of respective n- and p-type impurities through a sixth Si 3 N 4 layer having an effective thickness similar to the fifth layer; annealing the structure at about 800° C. for about 1-10 minutes; and depositing electrode metallizations atop the respective source and drain regions of the n- and p-type transistors.

Claim 9

The process of claim 6 wherein the wafer is a silicon wafer.

Claim 10

The process of claim 6 wherein the wafer is a GaAs wafer.

Claim 11

The process of claim 6 wherein the relative proportions of Al and Ga in the AlGaAs layers are defined by th formulate Al x Ga 1-x As where x is at least 0.3.