US4745455A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Silicon packages for power semiconductor devices
Assignee: Progress Bank
•
Filing: 1986-05-16
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Granted: 1988-05-17
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Expires: 2006-05-16
Abstract
Abstract A hermetically sealed package for a power semiconductor wafer is provided comprising substantially entirely silicon materials selected to have coefficients of thermal expansion closely matching that of the power semiconductor wafer. A semiconductor wafer such as a power diode comprises a layer of silicon material having first and second device regions on respective sides thereof. An electrically conductive cap and base, each including a layer of silicon material, are disposed in electrical contact with the first and second regions of the semiconductor device, respectively. An electrically insulative sidewall of silicon material surrounds the semiconductor wafer, is spaced from an edge thereof, and is bonded to the cap and base for hermetically sealing the package. An electrical passivant is disposed on an edge of the semiconductor wafer adjoining the first and second device regions for preventing electrical breakdown between the cap and base. An arc suppressant is disposed within the package between the semiconductor wafer edge and the sidewall for preventing electrical arcing between the base and cap.
Inventors
- 👤 II Homer H. Glascock
- 👤 Harold F. Webster
- 👤 Constantine A. Neugebauer
- 👤 Fadel A. Selim
- 👤 David L. Mueller
- 👤 Dante E. Piccone
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 01:49
CPC Classifications
H; H10; H10W; H10W76/00; H10W76/10; H10W76/12; H10W76/13; H10W76/138; H10W74/00; H10W74/10; H10W74/131; H10W74/137; H10W76/40; H10W76/42; H10W76/47
Claims Analysis
Total Claims: 49
Claim 1
Independent Claim
155 words
A hermetically sealed package having a silicon semiconductor wafer power device sealed therein; said semiconductor wafer comprising a layer of silicon material having first and second device regions on respective sides thereof; said package comprising: an electrically conductive silicon base bonded to said wafer in ohmic electrical contact with said first device region; an electrically conductive silicon cap bonded to said wafer in ohmic electrical contact with said second device region; an electrically insulative sidewall of silicon material surrounding said semiconductor wafer spaced from an edge thereof, said sidewall bonded to said silicon base and said silicon cap, said sidewall, base and cap together forming the hermetically sealed enclosure of said package; an electrical passivant disposed on said edge of said semiconductor wafer and adjoining said first and second device regions; and an arc suppressant disposed within said package and conforming to and substantially completely filling said space between said electrical passivant and said sidewall.
Claim 2
Dependent Claim
155 words
A hermetically sealed package having a silicon semiconductor wafer power device sealed therein; said semiconductor wafer comprising a layer of silicon material having first and second device regions on respective sides thereof; said package comprising: an electrically conductive silicon base bonded to said wafer in ohmic electrical contact with said first device region; an electrically conductive silicon cap bonded to said wafer in ohmic electrical contact with said second device region; an electrically insulative sidewall of silicon material surrounding said semiconductor wafer spaced from an edge thereof, said sidewall bonded to said silicon base and said silicon cap, said sidewall, base and cap together forming the hermetically sealed enclosure of said package; an electrical passivant disposed on said edge of said semiconductor wafer and adjoining said first and second device regions; and an arc suppressant disposed within said package and conforming to and substantially completely filling said space between said electrical passivant and said sidewall.
Claim 3
Dependent Claim
21 words
The package of claim 1 wherein said electrical passivant comprises a polyimide, a silicone room-temperature vulcanizing rubber (RTV), or amorphous silicon.
Claim 4
Dependent Claim
28 words
The package of claim 1 wherein said arc suppressant comprises alumina (Al 2 O 3 ), silicon dioxide (SiO 2 ), or a silicone room-temperature vulcanizing rubber (RTV).
Claim 5
Dependent Claim
31 words
The package of claim 1 wherein said base and cap are each fastened to said first and second device regions, respectively, with a bond comprising a solder or a diffusion bond.
Claim 6
Dependent Claim
16 words
The package of claim 4 wherein said solder comprises a lead alloy or an aluminum-silicon alloy.
Claim 7
Dependent Claim
11 words
The package of claim 4 wherein said diffusion bond comprises copper.
Claim 8
Dependent Claim
29 words
The package of claim 1 wherein said sidewall is hermetically bonded to said cap and said base with a bond comprising a solder, a diffusion bond, or glass frits.
Claim 9
Dependent Claim
16 words
The package of claim 7 wherein said solder comprises a lead alloy or an aluminum-silicon alloy.
Claim 10
Dependent Claim
11 words
The package of claim 7 wherein said diffusion bond comprises copper.
Claim 11
Dependent Claim
33 words
The package of claim 1 and further including an aperture in said package communicating with the gap between said sidewall and said semiconductor wafer edge for inserting said arc suppressant into said package.
Claim 12
Dependent Claim
39 words
The package of claim 1 further comprising a passageway extending between an external surface of said package and said arc-suppressant-filled space, said passageway itself being hermetically sealed to complete said hermetically sealed enclosure of said wafer in said package.
Claim 13
Dependent Claim
12 words
The package of claim 11 wherein said passageway is sealed with solder.
Claim 14
Dependent Claim
57 words
The package of claim 11 wherein said silicon base and said silicon cap both have substantially planar exterior surfaces and said passageway extends through either said silicon base or said silicon cap and said passageway is sealed by material which does not extend outward beyond the plane of said exterior surface of said base or cap, respectively.
Claim 15
Dependent Claim
185 words
A hermetically sealed package having a silicon semiconductor wafer power device sealed therein; said semiconductor wafer comprising a layer of silicon material having first and second device regions on respective sides thereof; said package comprising: an electrically conductive silicon base bonded to said wafer in ohmic electrical contact with said first device region; an electrically conductive silicon cap bonded to said wafer in ohmic electrical contact with said second device region; an electrically insulative sidewall of pre-molded silicon glass surrounding said semiconductor wafer and spaced from an edge thereof, said sidewall bonded to said silicon base and said silicon cap, said sidewall, base and cap together forming the hermetically sealed enclosure of said package, said glass selected to have a coefficient of thermal expansion close in value to that of said semiconductor wafer; an electrical passivant disposed on said edge of said semiconductor wafer and adjoining said first and second device regions; and an arc suppressant disposed within said package in said space between said electrical passivant and said sidewall and conforming to and substantially filling said space between said electrical passivant and said sidewall.
Claim 16
Dependent Claim
185 words
A hermetically sealed package having a silicon semiconductor wafer power device sealed therein; said semiconductor wafer comprising a layer of silicon material having first and second device regions on respective sides thereof; said package comprising: an electrically conductive silicon base bonded to said wafer in ohmic electrical contact with said first device region; an electrically conductive silicon cap bonded to said wafer in ohmic electrical contact with said second device region; an electrically insulative sidewall of pre-molded silicon glass surrounding said semiconductor wafer and spaced from an edge thereof, said sidewall bonded to said silicon base and said silicon cap, said sidewall, base and cap together forming the hermetically sealed enclosure of said package, said glass selected to have a coefficient of thermal expansion close in value to that of said semiconductor wafer; an electrical passivant disposed on said edge of said semiconductor wafer and adjoining said first and second device regions; and an arc suppressant disposed within said package in said space between said electrical passivant and said sidewall and conforming to and substantially filling said space between said electrical passivant and said sidewall.
Claim 17
Dependent Claim
19 words
The package of claim 14 wherein said electrical passivant comprises a polyimide, room-temperature vulcanizing rubber (RTV), or amorphous silicon.
Claim 18
Dependent Claim
26 words
The package of claim 14 wherein said arc suppressant comprises alumina (Al 2 O 3 ), silicon dioxide (SiO 2 ), or room-temperature vulcanizing rubber (RTV).
Claim 19
Dependent Claim
47 words
The package of claim 14 wherein said sidewall comprises a layer portion disposed between said cap and base and an edge portion extending outward beyond said cap and base and adapted for increasing the length of the leakage current creep path between said cap and said base.
Claim 20
Dependent Claim
15 words
The package of claim 14 wherein said cap and base each comprise highly-doped, low-resistivity silicon.
Claim 21
Dependent Claim
33 words
The package of claim 14 wherein said cap and base are doped with a dopant comprising aluminum (Al) or boron (B) or gallium (Ga) or arsenic (As) or phosphorous (P) or antimony (An).
Claim 22
Dependent Claim
32 words
The package of claim 14 wherein said cap and base each comprise high-purity, high-resistivity silicon including a plurality of vias extending therethrough, each of said vias filled with an electrically conductive material.
Claim 23
Dependent Claim
21 words
The package of claim 20 wherein said electrically conductive material comprises copper, lead (Pb) or an alloy of aluminum and silicon.
Claim 24
Dependent Claim
55 words
The package of claim 20 wherein: said semiconductor wafer edge extends past the edge of said cap; the edge of said base extends past said semiconductor wafer edge; and said sidewall has a generally L-shaped cross-section including one leg disposed in contact with said base and the other leg disposed in contact with said cap.
Claim 25
Dependent Claim
160 words
A hermetically sealed package having a silicon semiconductor wafer power device sealed therein; said semiconductor wafer comprising a layer of silicon material having first and second device regions on respective sides thereof; said package comprising: an electrically conductive silicon base bonded to said wafer in ohmic electrical contact with said first device region; an electrically conductive silicon cap bonded to said wafer in ohmic electrical contact with said second device region; an electrically insulative sidewall of high-purity, high-resistivity silicon surrounding said semiconductor wafer and spaced from an edge thereof, said sidewall bonded to said silicon base and said silicon cap, said sidewall, base and cap together forming the hermetically sealed enclosure of said package; an electrical passivant disposed on said edge of said semiconductor wafer and adjoining said first and second device regions; and an arc suppressant disposed within said package in said space between said electrical passivant and said sidewall and conforming to and substantially completely filling said space.
Claim 26
Dependent Claim
160 words
A hermetically sealed package having a silicon semiconductor wafer power device sealed therein; said semiconductor wafer comprising a layer of silicon material having first and second device regions on respective sides thereof; said package comprising: an electrically conductive silicon base bonded to said wafer in ohmic electrical contact with said first device region; an electrically conductive silicon cap bonded to said wafer in ohmic electrical contact with said second device region; an electrically insulative sidewall of high-purity, high-resistivity silicon surrounding said semiconductor wafer and spaced from an edge thereof, said sidewall bonded to said silicon base and said silicon cap, said sidewall, base and cap together forming the hermetically sealed enclosure of said package; an electrical passivant disposed on said edge of said semiconductor wafer and adjoining said first and second device regions; and an arc suppressant disposed within said package in said space between said electrical passivant and said sidewall and conforming to and substantially completely filling said space.
Claim 27
Dependent Claim
21 words
The package of claim 23 wherein said electrical passivant comprises a polyimide, a silicone roomtemperature vulcanizing rubber (RTV), or amorphous silicon.
Claim 28
Dependent Claim
26 words
The package of claim 23 wherein said arc suppressant comprises alumina (Al 2 O 3 ), silicon dioxide (SiO 2 ), or room-temperature vulcanizing rubber (RTV).
Claim 29
Dependent Claim
58 words
The package of claim 23 wherein: said cap and base each comprise highly-doped, low-resistivity silicon; and an insulative coating is disposed on the surface of the portions of said cap and base situated between said semiconductor wafer edge and the edge of said semiconductor package for increasing the leakage current creep path between said cap and said base.
Claim 30
Dependent Claim
23 words
The package of claim 26 wherein said insulative coating comprises alternate layers of semi-insulating polyoxygenated silicon (SIPOS) and silicon dioxide (SiO 2 ).
Claim 31
Dependent Claim
32 words
The package of claim 23 wherein said cap and base each comprise high-purity, high-resistivity silicon including a plurality of vias extending therethrough, each of said vias filled with an electrically conductive material.
Claim 32
Dependent Claim
21 words
The package of claim 28 wherein aid electrically conductive material comprises copper, lead (Pb) or an alloy of aluminum and silicon.
Claim 33
Dependent Claim
39 words
The package of claim 23 further comprising a passageway extending between an external surface of said package and said arc-suppressant-filled space, said passageway itself being hermetically sealed to complete said hermetically sealed enclosure of said wafer in said package.
Claim 34
Dependent Claim
12 words
The package of claim 30 wherein said passageway is sealed with solder.
Claim 35
Dependent Claim
57 words
The package of claim 30 wherein said silicon base and said silicon cap both have substantially planar exterior surfaces and said passageway extends through either said silicon base or said silicon cap and said passageway is sealed by material which does not extend outward beyond the plane of said exterior surface of said base or cap, respectively.
Claim 36
Dependent Claim
86 words
A sealed package having a silicon semiconductor power device wafer sealed therein comprising: electrically conductive silicon terminal layers bonded to said wafer in ohmic electrical contact with opposed major planar surfaces of said wafer, said layers overhanging the periphery of said wafer to form a peripheral channel intermediate said layers and outboard of said wafer, and an electrically insulative silicon sidewall located in said channel and bonded to said layers to form in cooperation therewith the enclosure of said package in which said wafer is sealed.
Claim 37
Dependent Claim
86 words
A sealed package having a silicon semiconductor power device wafer sealed therein comprising: electrically conductive silicon terminal layers bonded to said wafer in ohmic electrical contact with opposed major planar surfaces of said wafer, said layers overhanging the periphery of said wafer to form a peripheral channel intermediate said layers and outboard of said wafer, and an electrically insulative silicon sidewall located in said channel and bonded to said layers to form in cooperation therewith the enclosure of said package in which said wafer is sealed.
Claim 38
Dependent Claim
14 words
The package recited in claim 33 wherein said sidewall comprises a silicon glass material.
Claim 39
Dependent Claim
25 words
The package recited in claim 34 wherein said silicon glass material has a thermal coefficient of expansion substantially the same as that of said wafer.
Claim 40
Dependent Claim
21 words
The package recited in claim 33 further including an electrical passivant disposed on the edges of said wafer in said channel.
Claim 41
Dependent Claim
21 words
The package recited in claim 33 further including an arc suppressant disposed in said channel intermediate said wafer and said sidewall.
Claim 42
Dependent Claim
26 words
The package recited in claim 37 wherein one of said layers includes an opening communicating with said channel for inserting said arc suppressant into said channel.
Claim 43
Dependent Claim
39 words
The package of claim 37 further comprising a passageway extending between an external surface of said package and said arc-suppressant-filled space, said passageway itself being hermetically sealed to complete said hermetically sealed enclosure of said wafer in said package.
Claim 44
Dependent Claim
12 words
The package of claim 39 wherein said passageway is sealed with solder.
Claim 45
Dependent Claim
57 words
The package of claim 39 wherein said silicon base and said silicon cap both have substantially planar exterior surfaces and said passageway extends through either said silicon base or said silicon cap and said passageway is sealed by material which does not extend outward beyond the plane of said exterior surface of said base or cap, respectively.
Claim 46
Dependent Claim
24 words
The package recited in claim 33 wherein said layers are bonded to said wafer with a bond comprising a solder or a diffusion bond.
Claim 47
Dependent Claim
20 words
The package recited in claim 33 wherein within said channel said sidewall has substantially the same thickness as said wafer.
Claim 48
Dependent Claim
11 words
The package recited in claim 43 wherein: said sidewall is pre-molded.
Claim 49
Dependent Claim
11 words
The package recited in claim 33 wherein: said sidewall is pre-molded.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-05-17 | 1991-11-16 | 1992-05-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-05-17 | 1995-11-16 | 1996-05-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-05-17 | 1999-11-16 | 2000-05-17 | $7700.00 | Window Closed / Lapsed |