Glass passivated double beveled semiconductor device with partially spaced preform

Claim 2

A semiconductor device according to claim 1 in which said peripheral edges are polyhedral and said silicon semiconductive element exhibits a width along one of said contact surfaces in excess of 150 mils.

Claim 3

A semiconductor device according to claim 1 in which said second peripheral edge of said semiconductive element is positively beveled.

Claim 4

A semiconductor device according to claim 1 in which said beveled peripheral edge of said semiconductive element is negatively beveled in an amount sufficient to reduce the surface field gradient of said first junction adjacent said edge.

Claim 5

A semiconductor device according to claim 1 in which said beveled peripheral edge is negatively beveled adjacent said first junction and said second peripheral edge is positively beveled adjacent said second junction.

Claim 6

A semiconductor device according to claim 1 in which said preform is comprised of glass.

Claim 7

A semiconductor device according to claim 1 in which said preform is formed entirely of glass.

Claim 8

A semiconductor device according to claim 1 in which said glass passivant is a zinc borosilicate glass.

Claim 9

A semiconductor device according to claim 1 in which said contact means include a refractory metal backup plate having a thermal coefficient of expansion of less than 55 X 10 7/* C.

Claim 10

A semiconductor device according to claim 1 in which said one peripheral edge is said beveled peripheral edge.

Claim 11

A semiconductor device according to claim 1 in which said one peripheral edge is said second peripheral edge.

Claim 12

A thyristor comprising a silicon thyristor element having four sequentially arranged layers with adjacent layers being of opposite conductivity type, said layers forming three junctions therebetween, a first endmost of said layers lying adjacent a first contact surface and a remaining endmost of said layers lying adjacent a second contact surface, a beveled peripheral edge extending from said first contact surface and intersecting one of said junctions and a second peripheral edge extending from said second contact surface to said beveled edge and intersecting a second junction, and a package for encasing said thyristor element comprising a ceramic preform surrounding said thyristor element and having a first internal surface conforming to one of said peripheral edges of said element and spaced therefrom less than 1 mil, said preform having a thermal coefficient of expansion substantially matching that of said silicon thyristor element, a glass passivant bonding said one peripheral edge of said element to said conforming surface of said preform, said glass passivant also overlying a remaining of said peripheral edges and spaced from said preform adjacent said remaining peripheral edge, said glass passivant having a thermal coefficient of expansion in excess of that of silicon and below 45 X 10 7/* C., a firing temperature below that of said preform, and a maximum thickness less than 1 mil, and contact means associated with said first and second contact surfaces and sealingly associated with said preform.

Claim 13

A thyristor according to claim 13 in which said contact means include first main current carrying contact means bonded to a major portion of said first endmost layer adjacent said first contact and to said preform, gate contact means bonded to an intermediate layer of said thyristor element at said first contact surface at a location separated from said first main current carrying contact means by a junction, second main current carrying contact means bonded to said second contact surface and to said preform at a location spaced from said first contact means, and insulative means interposed between said gate contact means and said first main current carrying contact means.

Claim 14

A thyristor according to claim 13 in which said peripheral edges are annular and said silicon semiconductive element exhibits a diameter in excess of 150 mils.

Claim 15

A thyristor according to claim 13 in which said peripheral edges are polyhedral and said silicon semiconductive element exhibits a width alone one of said contact surfaces in excess of 150 mils.

Claim 16

A thyristor according to claim 13 in which said second peripheral edge of said thyristor element is positively beveled.

Claim 17

A thyristor according to claim 13 in which said beveled peripheral edge of said thyristor element is negatively beveled in an amount sufficient to reduce the surface field gradient of said first junction adjacent said edge.

Claim 18

A thyristor according to claim 13 in which said beveled peripheral edge is negatively beveled adjacent said first junction and said second peripheral edge is positively beveled adjacent said second junction.

Claim 19

A thyristor according to claim 13 in which said preform is comprised of glass.

Claim 20

A thyristor according to claim 13 in which said preform is formed entirely of glass.

Claim 21

A thyristor according to claim 13 in which said glass passivant is a zinc borosilicate glass.

Claim 22

A thyristor according to claim 13 in which said contact means include a refractory metal backup plate having a thermal coefficient of expansion of less than 55 X 10 7/* C.

Claim 23

A thyristor according to claim 13 in which said one peripheral edge is said beveled peripheral edge.

Claim 24

A thyristor according to claim 1 in which said one peripheral edge is said second peripheral edge.