Bipolar-transistor type random access memory having redundancy configuration

Claim 2

A semiconductor memory device including bipolar-transistors, comprising: a memory cell array; a redundancy memory cell array; means for receiving an address signal; means, operatively connected between said means for receiving an address signal and said memory cell array, for selecting a memory cell from said memory cell array in accordance with said address signal from said address receiving means; means, operatively connected to said means for receiving an address signal, for storing a defective address of a defective memory cell of said memory cell array, said defective address storing means comprising a plurality of 1-bit memory circuits of a diode type, each circuit corresponding to each bit of said defective address; and means, operatively connected to said means for storing a defective address and said means for receiving an address signal, for comparing said address signal from said means for receiving an address signal with said defective address from said means for storing a defective address so as to disable said memory cell selecting means and for selecting said redundancy memory cell array when said address signal coincides with said defective address.

Claim 3

A device as set forth in claim 1, wherein each of said 1-bit memory circuits comprises: first power supply means; second power supply means; write power supply means; at least three diode stages connected in a forward bias direction between said first power supply means second power supply means; current means connected between said at least three diode stages and said second power supply means, the connection of said current means and said at least three diode stages forming a node therebetween; a diode stage connected in a reverse bias direction between said write power supply means and said first power supply means; a short-circuited junction type PROM cell connected between said write power supply means and said node and having a short circuited and non-short circuited state; and a switching element, connected between said node and said second power supply means, for receiving one bit of said address signal and for generating a high or low potential at said node in accordance with the short-circuited or non-short-circuited state of said PROM cell.

Claim 4

A device as set forth in claim 2, wherein said current means comprises a current source.

Claim 5

A device as set forth in claim 2, wherein said current means comprises a resistor.

Claim 6

A device as set forth in claim 1, wherein each of said 1-bit memory circuits comprises: first power supply means; second power supply means; write power supply means; a first diode stage connected in a forward bias direction between said first power supply means and said second power supply means; a second diode stage including at least two diode stages connected in a forward bias direction between said first diode stage and said second power supply means; current means connected between said second diode stage and said second power supply means, the connection of said current means and said second diode stage forming a node therebetween; a short-circuited junction type PROM cell connected between said write power supply means and said node and having a short-circuited and non-short-circuited state; and a switching element, connected between said node and said second power supply means, for receiving one bit of said address signal and for generating a high or low potential at said node in accordance with the short-circuited or non-short-circuited state of said PROM cell.

Claim 7

A device as set forth in claim 5, wherein said current means comprises a current source.

Claim 8

A device as set forth in claim 5, wherein said current means comprises a resistor.

Claim 9

A device as set forth in claim 1, wherein each of said 1-bit memory circuits comprises: first power supply means; second power supply means; write power supply means; a first diode stage including at least three diode stages connected in a forward bias direction between said first power supply means and said second power supply means; a first resistor connected between said first diode stage and said second power supply means, the connection of said first resistor and said first diode stage forming a first node therebetween; a second diode stage connected between said first node and said second power supply means, and having the same conduction direction as said first diode stage; a second resistor connected between said second diode stage and said second power supply means, the connection of said second diode stage and said resistor forming a second node therebetween; a third diode stage connected in a reverse bias direction between said first power supply means and said write power supply means; a short-circuited junction type PROM cell connected between said write power supply means and said second node and having a short-circuited and non-short-circuited state; a switching element, connected between said second node and said second power supply means, for receiving one bit of said address signal; and output means, connected between said first and second nodes and said first and second power supply means, for detecting the difference in potential in accordance with the short-circuited or non-short-circuited state of said PROM cell.

Claim 10

A device as set forth in claim 1, wherein each of said 1-bit memory circuits comprises: first power supply means; second power supply means; write power supply means; a first diode stage including at least three diode stages connected in a forward bias direction between said first power supply means and said second power supply means; a first resistor connected between said first diode stage and said second power supply means, the connection of said first diode and said first resistor forming a first node therebetween; a second diode stage including at least four diodes stages connected in a forward bias direction between said first power supply means and said second power supply means; a second resistor connected between said second diode stage and said second power supply means, the connection of said second diode stage and said second resistor forming a second node therebetween; a third diode stage connected in a reverse bias direction between said first power supply means and said write power supply means; and a short-circuited-junction type PROM cell connected between said write power supply means and said second node and having a short-circuited and non-short-circuited state; a switching element, connected between said second node and said second power supply means, for receiving one bit of said address signal; and output means, connected between said first and second nodes and said first and second power supply means, for detecting the difference in potential in accordance with the short-circuited or non-short-circuited state of said PROM cell.

Claim 11

A device as set forth in claim 1, wherein each of said 1-bit memory circuits comprises: first power supply means; second power supply means; write power supply means; a first diode stage including at least two diode stages connected in a forward bias direction between said first power supply means and said second power supply means; a first resistor connected between said first diode stage and said second power supply means, the connection of said first resistor and said first diode stage forming a first node therebetween; a second diode stage connected to said first node, and having the same conduction direction as said first diode stage; a second resistor connected between said second diode stage and said second power supply means, the connection of said second diode stage and said second power supply means forming a second node therebetween; a resistor connected between said first power supply means and said write power supply means; a short-circuited-junction type PROM cell connected between said write power supply means and said second node and having a short-circuited state and non-short-circuited state; a switching element, connected between said second node and said second power supply means, for receiving one bit of said address signal; and output means, connected between said first and second nodes and said first and second power supply means, for detecting the difference in potential in accordance with the short-circuited or non-short-circuited state of said PROM cell.

Claim 12

A device as set forth in claim 1, wherein each of said 1-bit memory circuits comprises: first power supply means; second power supply means; write power supply means; a first diode stage connected in a forward bias direction to said first power supply means; a second diode stage including at least two diode stages connected to said first diode stage in a forward bias direction, forming a first node therebetween; a first resistor connected between said second diode stage and said second power supply means, the connection of said first resistor and said second diode stage forming a second node therebetween; a third diode stage connected to said second node, and having the same conduction direction as said second diode stage; a second resistor connected between said third diode stage and said second power supply means, the connection of said second resistor and said third diode stage forming a third node therebetween; a short-circuited junction type PROM cell connected between said write power supply means and said third node and having a short-circuited and non-short-circuited state; a switching element, connected between said third node and said second power supply means, for receiving one bit of said address signal; and output means connected between said second and third nodes and said first and second power supply means, for detecting the difference in potential in accordance with the short-circuited or non-short-circuited state of said PROM cell.

Claim 13

A device as set forth in claim 1, wherein each of said 1-bit memory circuits comprises: first power supply means; second power supply means; write power supply means; a first diode stage including at least two diode stages connected in a forward bias direction to said first power supply means; a first resistor connected between said first diode stage and said second power supply means, the connection of said first resistor and said first diode stage forming a first node therebetween; a second diode stage including at least three diode stages connected in a forward bias direction to said first power supply means; a second resistor connected between said second diode stage and said second power supply means, said connection of said second resistor and said second diode stage forming a second node therebetween; a third resistor connected between said first power supply means and said write power supply means; a short-circuited junction type PROM cell connected between said write power supply means and said second node and having a short-circuited and non-short-circuited state; a switching element, connected between said second node and said second power supply means, for receiving one bit of said address signal; and output means, connected to said first and second nodes, for detecting the difference in potential in accordance with the short-circuited or non-short-circuited state of said PROM cell.

Claim 14

An information memory device comprising: first power supply means; second power supply means 1 write power supply means; a first diode stage including at least three diodes stages connected in a forward bias direction between said first power supply means and said second power supply means; current means connected between said first diode stage and said second power supply means, the connection of said current source and said first diode stage forming a node therebetween; a second diode stage connected in a reverse bias direction between said write power supply means and said first power supply means; a short-circuited-junction type PROM cell connected between said write power supply means and said node and having a short-circuited and non-short-circuited state; and a switching element, connected between said node and said second power supply means for generating a high or low potential at said node in accordance with the short-circuited or non-short-circuited state of said PROM cell.

Claim 15

An information memory device comprising: first power supply means; second power supply means 1 write power supply means; a first diode stage including at least three diodes stages connected in a forward bias direction between said first power supply means and said second power supply means; current means connected between said first diode stage and said second power supply means, the connection of said current source and said first diode stage forming a node therebetween; a second diode stage connected in a reverse bias direction between said write power supply means and said first power supply means; a short-circuited-junction type PROM cell connected between said write power supply means and said node and having a short-circuited and non-short-circuited state; and a switching element, connected between said node and said second power supply means for generating a high or low potential at said node in accordance with the short-circuited or non-short-circuited state of said PROM cell.

Claim 16

A device as set forth in claim 13, wherein said current means comprises a current source.

Claim 17

A device as set forth in claim 13, wherein said current means comprises a resistor.

Claim 18

An information memory device comprising: first power supply means; second power supply means; write power supply means; a first diode stage including at least two diode stages connected in a forward bias direction between said first power supply means and said second power supply means; current means connected between said first diode stage and said second power supply means, the connection of said current means and said first diode stage forming a node therebetween; a resistor connected between said write power supply means and said first power supply means; a short-circuited-junction type PROM cell connected between said write power supply means and said node and having a short-circuited and non-short-circuited state; and a switching element, connected between said node and said second power supply means, for generating a high or low potential at said node in accordance with the short-circuited or non-short-circuited state of said PROM cell.

Claim 19

An information memory device comprising: first power supply means; second power supply means; write power supply means; a first diode stage including at least two diode stages connected in a forward bias direction between said first power supply means and said second power supply means; current means connected between said first diode stage and said second power supply means, the connection of said current means and said first diode stage forming a node therebetween; a resistor connected between said write power supply means and said first power supply means; a short-circuited-junction type PROM cell connected between said write power supply means and said node and having a short-circuited and non-short-circuited state; and a switching element, connected between said node and said second power supply means, for generating a high or low potential at said node in accordance with the short-circuited or non-short-circuited state of said PROM cell.

Claim 20

An information memory device comprising: first power supply means; second power supply means; write power supply means; a first diode stage connected in a forward bias direction to said first power supply means; a second diode stage including at least two diode stages connected in a forward bias direction between said first diode stage and said second power supply means, the connection of said first diode stage and said second diode stage forming a first node therebetween, the connection of said second diode stage and said second power supply means forming a second node therebetween; current means connected between said second node and said second power supply means; a short-circuited junction type PROM cell connected between said write power supply means and said second node and having a short-circuited state and non-short-circuited state; and a switching element, connected between said second node and said second power supply means for generating a high or low potential at said second node in accordance with the short-circuited or non-short-circuited state of said PROM cell.

Claim 21

An information memory device comprising: first power supply means; second power supply means; write power supply means; a first diode stage connected in a forward bias direction to said first power supply means; a second diode stage including at least two diode stages connected in a forward bias direction between said first diode stage and said second power supply means, the connection of said first diode stage and said second diode stage forming a first node therebetween, the connection of said second diode stage and said second power supply means forming a second node therebetween; current means connected between said second node and said second power supply means; a short-circuited junction type PROM cell connected between said write power supply means and said second node and having a short-circuited state and non-short-circuited state; and a switching element, connected between said second node and said second power supply means for generating a high or low potential at said second node in accordance with the short-circuited or non-short-circuited state of said PROM cell.

Claim 22

A device as set forth in claim 17, wherein said current means comprises a current source.

Claim 23

A device as set forth in claim 17, wherein said current means comprises a resistor.

Claim 24

An information memory device comprising: first power supply means; second power supply means; write power supply means; a first diode stage including at least three diode stages connected in a forward bias direction to said first power supply means; a first resistor connected between said first diode stage and said second power supply means, the connection of said first diode stage and said first resistor forming a first node therebetween; a second diode stage connected to said first node, and having the same conduction direction as said first diode stage; a second resistor connected between said second diode stage and said second power supply means, the connection of said second diode stage and said second resistor forming a second connection node therebetween; a third diode stage connected in a reverse bias direction between said first power supply means and said write power supply means; a short-circuited junction type PROM cell connected between said write power supply means and said second node and having a short-circuited state and non-short-circuited state; a switching element connected between said second node and said second power supply means; and output means, connected between said first and second nodes, for detecting the difference in potential in accordance with the short-circuited or non-short-circuited stage of said PROM cell.

Claim 25

An information memory device comprising: first power supply means; second power supply means; write power supply means; a first diode stage including at least three diode stages connected in a forward bias direction to said first power supply means; a first resistor connected between said first diode stage and said second power supply means, the connection of said first diode stage and said first resistor forming a first node therebetween; a second diode stage connected to said first node, and having the same conduction direction as said first diode stage; a second resistor connected between said second diode stage and said second power supply means, the connection of said second diode stage and said second resistor forming a second connection node therebetween; a third diode stage connected in a reverse bias direction between said first power supply means and said write power supply means; a short-circuited junction type PROM cell connected between said write power supply means and said second node and having a short-circuited state and non-short-circuited state; a switching element connected between said second node and said second power supply means; and output means, connected between said first and second nodes, for detecting the difference in potential in accordance with the short-circuited or non-short-circuited stage of said PROM cell.

Claim 26

An information memory device comprising: first power supply means; second power supply means; write power supply means; a first diode stage including at least three diode stages connected in a forward bias direction to said first power supply means and said first node; a first resistor connected between said first diode stage and said second power supply means, the connection of said first diode stage and said first resistor forming a first node therebetween; a second diode stage including at least four diodes connected in a forward bias direction to said first power supply means; a second resistor connected between said second diode stage and said second power supply means, the connection of said second diode stage and said second resistor forming a second node therebetween; a third diode stage connected in a reverse bias direction between said first power supply means and said write power supply means; a short-circuited junction type PROM cell connected between said write power supply means and said second node and having a short-circuited state and non-short-circuited state; a switching element, connected between said second node and said second power supply means; and output means, connected between said first and second nodes and said first and second power supply means, for detecting a potential difference in accordance with the short-circuited or non-short-circuited state of said PROM cell.

Claim 27

An information memory device comprising: first power supply means; second power supply means; write power supply means; a first diode stage including at least three diode stages connected in a forward bias direction to said first power supply means and said first node; a first resistor connected between said first diode stage and said second power supply means, the connection of said first diode stage and said first resistor forming a first node therebetween; a second diode stage including at least four diodes connected in a forward bias direction to said first power supply means; a second resistor connected between said second diode stage and said second power supply means, the connection of said second diode stage and said second resistor forming a second node therebetween; a third diode stage connected in a reverse bias direction between said first power supply means and said write power supply means; a short-circuited junction type PROM cell connected between said write power supply means and said second node and having a short-circuited state and non-short-circuited state; a switching element, connected between said second node and said second power supply means; and output means, connected between said first and second nodes and said first and second power supply means, for detecting a potential difference in accordance with the short-circuited or non-short-circuited state of said PROM cell.

Claim 28

An information memory device comprising: first power supply means; second power supply means; write power supply means; a first diode stage including at least two diode stages connected in a forward bias direction to said first power supply means; a first resistor connected between said first diode stage and said second power supply means, the connection of said first resistor and said first diode stage forming a first node therebetween; a second diode stage connected to said first node, and having the same conduction direction as said first diode stage; a second resistor connected between said second diode stage and said second power supply means, the connection of said second diode stage and said second resistor forming a second node therebetween; a resistor connected between said first power supply means and said write power supply means; a short-circuited junction type PROM cell connected between said write power supply means and said second node and having a short-circuited state and non-short-circuited state; a switching element, connected between said second node and said second power supply means; and output means, connected between said first and second nodes, for detecting a difference in potential in accordance with the short-circuited or non-short-circuited state of said PROM cell.

Claim 29

An information memory device comprising: first power supply means; second power supply means; write power supply means; a first diode stage including at least two diode stages connected in a forward bias direction to said first power supply means; a first resistor connected between said first diode stage and said second power supply means, the connection of said first resistor and said first diode stage forming a first node therebetween; a second diode stage connected to said first node, and having the same conduction direction as said first diode stage; a second resistor connected between said second diode stage and said second power supply means, the connection of said second diode stage and said second resistor forming a second node therebetween; a resistor connected between said first power supply means and said write power supply means; a short-circuited junction type PROM cell connected between said write power supply means and said second node and having a short-circuited state and non-short-circuited state; a switching element, connected between said second node and said second power supply means; and output means, connected between said first and second nodes, for detecting a difference in potential in accordance with the short-circuited or non-short-circuited state of said PROM cell.

Claim 30

An information memory device comprising: first power supply means; second power supply means; write power supply means; a first diode stage connected in a forward bias direction to said first power supply means; a second diode stage including at least two diode stages connected in a forward bias direction to said first diode stage, forming a first connection node therebetween; a first resistor connected between said second diode stage and said second power supply means, the connection of said second diode stage and said first resistor forming a second node therebetween; a third diode stage connected to said second node, and having the same conduction direction as said second diode stage; a second resistor connected between said third diode stage and said second power supply means, the connection of said third diode stage and said second resistor forming a third node therebetween; a short-circuited junction type PROM cell connected between said write power supply means and said third node and having a short-circuited state and non-short-circuited state; a switching element, connected between said third node and said second power supply means; and output means, connected between said second and third nodes and said first and second power supply means, for detecting a difference in potential in accordance with the short-circuited or non-short-circuited state of said PROM cell.

Claim 31

An information memory device comprising: first power supply means; second power supply means; write power supply means; a first diode stage connected in a forward bias direction to said first power supply means; a second diode stage including at least two diode stages connected in a forward bias direction to said first diode stage, forming a first connection node therebetween; a first resistor connected between said second diode stage and said second power supply means, the connection of said second diode stage and said first resistor forming a second node therebetween; a third diode stage connected to said second node, and having the same conduction direction as said second diode stage; a second resistor connected between said third diode stage and said second power supply means, the connection of said third diode stage and said second resistor forming a third node therebetween; a short-circuited junction type PROM cell connected between said write power supply means and said third node and having a short-circuited state and non-short-circuited state; a switching element, connected between said third node and said second power supply means; and output means, connected between said second and third nodes and said first and second power supply means, for detecting a difference in potential in accordance with the short-circuited or non-short-circuited state of said PROM cell.

Claim 32

An information memory device comprising: first power supply means; second power supply means; write power supply means; a first diode stage including at least two diode stages connected in a forward bias direction to said first power supply means; a first resistor connected between said first diode stage and said second power supply means, the connection of said first resistor and said first diode stage forming a node therebetween; a second diode stage including at least three diode stages connected in a forward bias direction to said first power supply means; a second resistor connected between said second diode stage and said second power supply means, the connection of said second diode stage and said second resistor forming a node therebetween; a resistor connected in a reverse bias direction between said first power supply means and said write power supply means; and a short-circuited junction type PROM cell connected between said write power supply means and said second node and having a short-circuited and non-short-circuited state; a switching element, connected between said second node and said second power supply means; and output means, connected between said first and second nodes and said first and second power supply means, for detecting the difference in potential in accordance with the short-circuited or non-short-circuited state of said PROM cell.

Claim 33

An information memory device comprising: first power supply means; second power supply means; write power supply means; a first diode stage including at least two diode stages connected in a forward bias direction to said first power supply means; a first resistor connected between said first diode stage and said second power supply means, the connection of said first resistor and said first diode stage forming a node therebetween; a second diode stage including at least three diode stages connected in a forward bias direction to said first power supply means; a second resistor connected between said second diode stage and said second power supply means, the connection of said second diode stage and said second resistor forming a node therebetween; a resistor connected in a reverse bias direction between said first power supply means and said write power supply means; and a short-circuited junction type PROM cell connected between said write power supply means and said second node and having a short-circuited and non-short-circuited state; a switching element, connected between said second node and said second power supply means; and output means, connected between said first and second nodes and said first and second power supply means, for detecting the difference in potential in accordance with the short-circuited or non-short-circuited state of said PROM cell.

Claim 34

A semiconductor memory device including bipolar-transistors, comprising: a memory cell array; a redundancy memory cell array; means for receiving an address signal; means, operatively connected between said means for receiving an address signal and said memory cell array, for selecting a memory cell from said memory cell array in accordance with said address signal from said address receiving means; means, operatively connected to said means for receiving an address signal, for storing a defective address of a defective memory cell of said memory cell array, said defective address storing means comprising a plurality of 1-bit memory circuits of a diode type, each circuit corresponding to each bit of said defective address, each of said 1-bit memory circuits including: first power supply means; second power supply means; write power supply means; at least two diode stages connected in a forward bias direction between said first power supply means and said second power supply means; current means connected between said at least two diode stages and said second power supply means, the connection of said current means and said at least two diode stages forming a node therebetween; a short-circuited junction type PROM cell connected between said write power supply means and said node and having a short-circuited and non-short-circuited state; and a switching element, connected between said node and said second power supply means, for receiving one bit of said address signal, and for generating a high or low-potential at said node in accordance with the short-circuited or non-short-circuited state of said PROM cell; and means, operatively connected to said means for storing a defective address and said means for receiving an address signal, for comparing said address signal from said means for receiving an address signal with said defective address from said means for storing a defective address and disabling said memory cell selecting means and for selecting said redundancy memory cell array when said address signal coincides with said defective address.

Claim 35

A semiconductor memory device including bipolar-transistors, comprising: a memory cell array; a redundancy memory cell array; means for receiving an address signal; means, operatively connected between said means for receiving an address signal and said memory cell array, for selecting a memory cell from said memory cell array in accordance with said address signal from said address receiving means; means, operatively connected to said means for receiving an address signal, for storing a defective address of a defective memory cell of said memory cell array, said defective address storing means comprising a plurality of 1-bit memory circuits of a diode type, each circuit corresponding to each bit of said defective address, each of said 1-bit memory circuits including: first power supply means; second power supply means; write power supply means; at least two diode stages connected in a forward bias direction between said first power supply means and said second power supply means; current means connected between said at least two diode stages and said second power supply means, the connection of said current means and said at least two diode stages forming a node therebetween; a short-circuited junction type PROM cell connected between said write power supply means and said node and having a short-circuited and non-short-circuited state; and a switching element, connected between said node and said second power supply means, for receiving one bit of said address signal, and for generating a high or low-potential at said node in accordance with the short-circuited or non-short-circuited state of said PROM cell; and means, operatively connected to said means for storing a defective address and said means for receiving an address signal, for comparing said address signal from said means for receiving an address signal with said defective address from said means for storing a defective address and disabling said memory cell selecting means and for selecting said redundancy memory cell array when said address signal coincides with said defective address.

Claim 36

A device as set forth in claim 25, wherein said current means comprises a current source.

Claim 37

A device as set forth in claim 25, wherein said current means comprises a resistor.

Claim 38

A semiconductor memory device including bipolar-transistors, comprising: a memory cell array; a redundancy memory cell array; means for receiving an address signal; means, operatively connected between said means for receiving an address signal and said memory cell array, for selecting a memory cell from said memory cell array in accordance with said address signal from said address receiving means; means, operatively connected to said means for receiving an address signal, for storing a defective address of a defective memory cell of said memory cell array, said defective address storing means comprising a plurality of 1-bit memory circuits of a diode type, each circuit corresponding to each bit of said defective address; means, operatively connected to said means for storing a defective address and said means for receiving an address signal, for comparing said signal from said means for receiving an address signal with said defective address from said means for storing a defective address so as to disable said memory cell selecting means and for selecting said redundancy memory cell array when said address signal coincides with said defective address; and means, connected between said means for receiving an address signal and said means for storing a defective address, for transmitting said address signal to said means for storing a defective address during a defective address writing mode and hindering transmission of said address signal to said means for storing a defective address during a normal address writing mode.

Claim 39

A semiconductor memory device including bipolar-transistors, comprising: a memory cell array; a redundancy memory cell array; means for receiving an address signal; means, operatively connected between said means for receiving an address signal and said memory cell array, for selecting a memory cell from said memory cell array in accordance with said address signal from said address receiving means; means, operatively connected to said means for receiving an address signal, for storing a defective address of a defective memory cell of said memory cell array, said defective address storing means comprising a plurality of 1-bit memory circuits of a diode type, each circuit corresponding to each bit of said defective address; means, operatively connected to said means for storing a defective address and said means for receiving an address signal, for comparing said signal from said means for receiving an address signal with said defective address from said means for storing a defective address so as to disable said memory cell selecting means and for selecting said redundancy memory cell array when said address signal coincides with said defective address; and means, connected between said means for receiving an address signal and said means for storing a defective address, for transmitting said address signal to said means for storing a defective address during a defective address writing mode and hindering transmission of said address signal to said means for storing a defective address during a normal address writing mode.

Claim 40

A device as set forth in claim 28, further comprising switching means connected to said address receiving means and connected to receive the address signal, said switching means including: level shift means for reducing the output amplitude of said address receiving means so that the input amplitude of said defective address storing means is smaller than the output amplitude of said defective address storing means.

Claim 41

A device as set forth in claim 29, wherein said level shift means includes one or more stages of emitter-followers, diodes, or resistors.