Patent US4943328A successfully refreshed from Google Patents.
Patent US5095384A successfully refreshed from Google Patents.
Patent US4743847A successfully refreshed from Google Patents.
US4743847A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Printed circuit conductor test system
Assignee: International Business Machines Corp
•
Filing: 1987-06-17
•
Granted: 1988-05-10
•
Expires: 2007-06-17
Abstract
Abstract A system for testing conductor lines in a printed circuit board includes circuitry for the burning out of constricted regions of the printed circuit lines so as to insure that such defects are noticed. The system includes circuitry for measuring the resistance in a path through a printed circuit line under test and including connecting circuitry to a generator of an electrical pulse. A resistor network and switching circuitry is employed for adjusting the resistance of the path through a desired value. The electrical pulse is generated by the discharge of a capacitor previously charged to a predetermined value of voltage, the discharge occurring via a pulsing circuit switch which limits the duration of the pulse through a predetermined value of sufficiently short duration to prevent damage to the circuit board associated with excessive heating. Monitoring circuitry including a peak detector and comparators is employed for sensing a sudden change in test current amplitude, as well as test currents having amplitudes of an acceptable range, for terminating the test current pulse prematurely upon an indication of burnout, thereby to protect the circuit board.
Inventors
- 👤 James E. Frushour
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 21:20
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/2801; G01R31/281; G01R31/2812; G01R31/2805; G01R31/2817
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
182 words
A method for testing current capacity of a printed line conductor in a printed circuit board comprising: constructing a series resistance path with a conductor to be tested, said resistance path including a current sensing resistor; establishing a time frame for monitoring a test of the conductor; applying a test current pulse via said resistance path to said conductor within said time frame; monitoring the amplitude of current flowing in the sensing resistor during said time frame to determine a condition of current conduction in said conductor; and regulating the current pulse in accordance with said condition; and wherein said applying of a pulse includes a step of charging a capacitor with a predetermined amount of energy sufficiently small to prevent damage to said circuit board, said applying of a pulse including a step of imparting sufficient energy to said current pulse to induce burnout of a constricted cross section of a printed line conductor in a printed circuit board, said applying of a pulse further including a step of generating a voltage pulse by discharging a capacitor into said resistance path.
Claim 2
Independent Claim
182 words
A method for testing current capacity of a printed line conductor in a printed circuit board comprising: constructing a series resistance path with a conductor to be tested, said resistance path including a current sensing resistor; establishing a time frame for monitoring a test of the conductor; applying a test current pulse via said resistance path to said conductor within said time frame; monitoring the amplitude of current flowing in the sensing resistor during said time frame to determine a condition of current conduction in said conductor; and regulating the current pulse in accordance with said condition; and wherein said applying of a pulse includes a step of charging a capacitor with a predetermined amount of energy sufficiently small to prevent damage to said circuit board, said applying of a pulse including a step of imparting sufficient energy to said current pulse to induce burnout of a constricted cross section of a printed line conductor in a printed circuit board, said applying of a pulse further including a step of generating a voltage pulse by discharging a capacitor into said resistance path.
Claim 3
Dependent Claim
32 words
A method according to claim 1 wherein said monitoring is accomplished by generating timing signals, and by a logical combination of the instantaneous amplitude of said current pulse with said timing signals.
Claim 4
Dependent Claim
22 words
A method according to claim 1 wherein said constructing of the path is accomplished by a measuring of resistance in said path.
Claim 5
Dependent Claim
35 words
A method according to claim 3 wherein said step of measuring includes a step of transmitting along said path a pulse of current having an amplitude less than the amplitude of said test current pulse.
Claim 6
Dependent Claim
22 words
A method according to claim 4 wherein said constructing further comprises a setting of a desired value of resistance to said path.
Claim 7
Dependent Claim
65 words
A method according to claim 4 wherein said monitoring of amplitude is accomplished as a function of time to determine the presence of a variation in current amplitude within the duration of said current pulse; said monitoring including a step of observing a stepwise shift in current amplitude from a first current level to a second current level within the druation of said current pulse.
Claim 8
Independent Claim
156 words
A method for testing current capacity of a printed line conductor in a printed circuit board comprising: constructing a series resistance path with a conductor to be tested, said resistance path including a current sensing resistor; establishing a time frame for monitoring a test of the conductor; applying a test current pulse via said resistance path to said conductor within said time frame; monitoring the amplitude of current flowing in the snesing resistor during said time frame to determine a condition of current conduction in said conductor; regulating the current pulse in accordance with said condition; and wherein said monitoring of amplitude is accomplished as a function of time to determine the presence of a variation in current amplitude within the duration of said current pulse; said monitoring including a step of observing a stepwise shift in current amplitude from a first current level to a second current level within the duration of said current pulse.
Claim 9
Independent Claim
156 words
A method for testing current capacity of a printed line conductor in a printed circuit board comprising: constructing a series resistance path with a conductor to be tested, said resistance path including a current sensing resistor; establishing a time frame for monitoring a test of the conductor; applying a test current pulse via said resistance path to said conductor within said time frame; monitoring the amplitude of current flowing in the snesing resistor during said time frame to determine a condition of current conduction in said conductor; regulating the current pulse in accordance with said condition; and wherein said monitoring of amplitude is accomplished as a function of time to determine the presence of a variation in current amplitude within the duration of said current pulse; said monitoring including a step of observing a stepwise shift in current amplitude from a first current level to a second current level within the duration of said current pulse.
Claim 10
Dependent Claim
22 words
A method according to claim 7 wherein said monitoring of amplitude includes a step of detecting peak amplitude of said current pulse.
Claim 11
Dependent Claim
61 words
A method according to claim 9 wherein said step of monitoring further includes an offsetting of said peak amplitude to establish a reference signal, said monitoring further including a comparing of the instantaneous amplitude of said current pulse with said reference signal to provide a comparison signal indicative of said variation of current amplitude within the duration of said current pulse.
Claim 12
Dependent Claim
46 words
A method according to claim 9 wherein said monitoring is accomplished by generating timing signals, and by a logical combination of said comparison signal with said timing signals to provide an indication of said condition and to provide a regulating signal for said step of regulating.
Claim 13
Dependent Claim
56 words
A method according to claim 10 wherein said generating of timing signals is accomplished by generating timing signals which bracket predetermined portions of said current pulse, one of said timing signals beginning after the leading edge of said current pulse, and a second of said timing signals terminating before a trailing edge of said current pulse.
Claim 14
Dependent Claim
28 words
A method according to claim 10 wherein said regulating signal provides for a termination of said current pulse upon the occurrence of a defective condition in said conductor.
Claim 15
Dependent Claim
28 words
A method according to claim 10 wherein said monitoring is accomplished further by a logical combination of the instantaneous amplitude of said current pulse with said timing signals.
Claim 16
Independent Claim
314 words
A system for testing current capacity of a printed line conductor comprising: means for applying a test current pulse to said conductor, said pulse having sufficient power over a predetermined interval of time to burn out a constricted region of a printed line conductor having a cross sectional area less than a predetermined amount of area; means for monitoring the waveform of a test pulse of current flowing in said conductor as a function of time to determine a condition of said conductor, said waveform varying in accordance with the condition of said conductor, said monitoring means providing a signal designating a type of waveform; means responsive to said of said monitoring means for terminating a flow of the current piror to the end of said predetermined interval when the waveform of said current pulse indicates the occurrence of a burnout in said conductor; and wherein said current applying means comprises means for generating a voltage pulse, and a resistance network interconnecting said generating means with said conductor; said resistance network includes a current sensing resistor serially connected with said conductor, said monitoring means being responsive to a voltage developed across said sensing resistor by said current pulse; said conductor is a strip line conductor disposed on a printed circuit board, and the resistance of said network includes resistance of said conductor and resistance of said sensing resistor, said system further comprising means for measuring the resistance of said network and means for adjusting the resistance of said network to a predetermined value permitting burnout of a constricted region of a strip line conductor without incurring significant damage to said printed circuit board; and unsaid generating means comprises a capacitor, means for charging said capacitor with a predetermined voltage, and pulsign means for discharging said capacitor, said pulsing means applying a pulse of electric energy from said capacitor to said conductor via said network.
Claim 17
Independent Claim
314 words
A system for testing current capacity of a printed line conductor comprising: means for applying a test current pulse to said conductor, said pulse having sufficient power over a predetermined interval of time to burn out a constricted region of a printed line conductor having a cross sectional area less than a predetermined amount of area; means for monitoring the waveform of a test pulse of current flowing in said conductor as a function of time to determine a condition of said conductor, said waveform varying in accordance with the condition of said conductor, said monitoring means providing a signal designating a type of waveform; means responsive to said of said monitoring means for terminating a flow of the current piror to the end of said predetermined interval when the waveform of said current pulse indicates the occurrence of a burnout in said conductor; and wherein said current applying means comprises means for generating a voltage pulse, and a resistance network interconnecting said generating means with said conductor; said resistance network includes a current sensing resistor serially connected with said conductor, said monitoring means being responsive to a voltage developed across said sensing resistor by said current pulse; said conductor is a strip line conductor disposed on a printed circuit board, and the resistance of said network includes resistance of said conductor and resistance of said sensing resistor, said system further comprising means for measuring the resistance of said network and means for adjusting the resistance of said network to a predetermined value permitting burnout of a constricted region of a strip line conductor without incurring significant damage to said printed circuit board; and unsaid generating means comprises a capacitor, means for charging said capacitor with a predetermined voltage, and pulsign means for discharging said capacitor, said pulsing means applying a pulse of electric energy from said capacitor to said conductor via said network.
Claim 18
Dependent Claim
37 words
A system according to claim 14 further comprising timing means for activating said pulsing means to provide said pulse with a predetermined duration so as to prevent the dissipation of excessive energy in said printed circuit board.
Claim 19
Dependent Claim
38 words
A system according to claim 15 further comprising logic means interconnecting said timing means and said terminating means with said pulsing means to permit termination of said current pulse by said temrinating means prior to said predetermined duration.
Claim 20
Dependent Claim
24 words
A system according to claim 16 further comprising selector means for selectively connecting said measuring means and said pulsing means to said resistance network.
Claim 21
Dependent Claim
22 words
A system according to claim 14 wherein said measuring means comprises means for transmitting a measuring pulse of current through said conductor.
References Cited (Backward Citations)
US2605322A
Cited
US3392332A
Cited
US3392324A
Cited
US3373356A
Cited
US3366055A
Cited
US3622882A
Cited
US3652929A
Cited
US3772590A
Cited
US3930304A
Cited
US4140965A
Cited
US4213087A
Cited
US4377782A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-05-10 | 1991-11-09 | 1992-05-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-05-10 | 1995-11-09 | 1996-05-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-05-10 | 1999-11-09 | 2000-05-10 | $7700.00 | Window Closed / Lapsed |